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[86.188.11.239]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bd7031f3sm213289985e9.6.2026.02.27.14.04.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 14:04:12 -0800 (PST) Message-ID: Subject: Re: [PATCH v8 09/18] arm64: dts: qcom: x1e80100: Add CCI definitions From: Christopher Obbard To: Bryan O'Donoghue , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio , Vladimir Zapolskiy , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio Date: Fri, 27 Feb 2026 22:04:11 +0000 In-Reply-To: <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-9-95517393bcb2@linaro.org> References: <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-0-95517393bcb2@linaro.org> <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-9-95517393bcb2@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-8 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Bryan, On Wed, 2026-02-25 at 15:11 +0000, Bryan O'Donoghue wrote: > Add in two CCI buses. >=20 > One bus has two CCI bus master pinouts: > cci_i2c_sda0 =3D gpio101 > cci_i2c_scl0 =3D gpio102 >=20 > cci_i2c_sda1 =3D gpio103 > cci_i2c_scl1 =3D gpio104 >=20 > The second bus has two CCI bus master pinouts: > cci_i2c_sda2 =3D gpio105 > cci_i2c_scl2 =3D gpio106 >=20 > aon_cci_i2c_sda3 =3D gpio235 > aon_cci_i2c_scl3 =3D gpio236 >=20 > Reviewed-by: Konrad Dybcio > Reviewed-by: Vladimir Zapolskiy > Signed-off-by: Bryan O'Donoghue > --- Reviewed-by: Christopher Obbard Tested-by: Christopher Obbard > arch/arm64/boot/dts/qcom/hamoa.dtsi | 149 ++++++++++++++++++++++++++++++= ++++++ > 1 file changed, 149 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qc= om/hamoa.dtsi > index f96411f481305..38f9da6ad9ca5 100644 > --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi > +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi > @@ -5465,6 +5465,83 @@ videocc: clock-controller@aaf0000 { > #power-domain-cells =3D <1>; > }; > =20 > + cci0: cci@ac15000 { > + compatible =3D "qcom,x1e80100-cci", "qcom,msm8996-cci"; > + reg =3D <0 0x0ac15000 0 0x1000>; > + > + interrupts =3D ; > + > + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_0_CLK>; > + clock-names =3D "camnoc_axi", > + "cpas_ahb", > + "cci"; > + > + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + pinctrl-0 =3D <&cci0_default>; > + pinctrl-1 =3D <&cci0_sleep>; > + pinctrl-names =3D "default", "sleep"; > + > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + status =3D "disabled"; > + > + cci0_i2c0: i2c-bus@0 { > + reg =3D <0>; > + clock-frequency =3D <1000000>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + cci0_i2c1: i2c-bus@1 { > + reg =3D <1>; > + clock-frequency =3D <1000000>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + }; > + > + cci1: cci@ac16000 { > + compatible =3D "qcom,x1e80100-cci", "qcom,msm8996-cci"; > + reg =3D <0 0x0ac16000 0 0x1000>; > + > + interrupts =3D ; > + > + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_1_CLK>; > + clock-names =3D "camnoc_axi", > + "cpas_ahb", > + "cci"; > + > + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + pinctrl-0 =3D <&cci1_default>; > + pinctrl-1 =3D <&cci1_sleep>; > + pinctrl-names =3D "default", "sleep"; > + > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + status =3D "disabled"; > + > + cci1_i2c0: i2c-bus@0 { > + reg =3D <0>; > + clock-frequency =3D <1000000>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + cci1_i2c1: i2c-bus@1 { > + reg =3D <1>; > + clock-frequency =3D <1000000>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + }; > =20 > camcc: clock-controller@ade0000 { > compatible =3D "qcom,x1e80100-camcc"; > @@ -6116,6 +6193,78 @@ tlmm: pinctrl@f100000 { > gpio-ranges =3D <&tlmm 0 0 239>; > wakeup-parent =3D <&pdc>; > =20 > + cci0_default: cci0-default-state { > + cci0_i2c0_default: cci0-i2c0-default-pins { > + /* cci_i2c_sda0, cci_i2c_scl0 */ > + pins =3D "gpio101", "gpio102"; > + function =3D "cci_i2c"; > + drive-strength =3D <2>; > + bias-pull-up; > + }; > + > + cci0_i2c1_default: cci0-i2c1-default-pins { > + /* cci_i2c_sda1, cci_i2c_scl1 */ > + pins =3D "gpio103", "gpio104"; > + function =3D "cci_i2c"; > + drive-strength =3D <2>; > + bias-pull-up; > + }; > + }; > + > + cci0_sleep: cci0-sleep-state { > + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { > + /* cci_i2c_sda0, cci_i2c_scl0 */ > + pins =3D "gpio101", "gpio102"; > + function =3D "cci_i2c"; > + drive-strength =3D <2>; > + bias-pull-down; > + }; > + > + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { > + /* cci_i2c_sda1, cci_i2c_scl1 */ > + pins =3D "gpio103", "gpio104"; > + function =3D "cci_i2c"; > + drive-strength =3D <2>; > + bias-pull-down; > + }; > + }; > + > + cci1_default: cci1-default-state { > + cci1_i2c0_default: cci1-i2c0-default-pins { > + /* cci_i2c_sda2, cci_i2c_scl2 */ > + pins =3D "gpio105", "gpio106"; > + function =3D "cci_i2c"; > + drive-strength =3D <2>; > + bias-pull-up; > + }; > + > + cci1_i2c1_default: cci1-i2c1-default-pins { > + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ > + pins =3D "gpio235", "gpio236"; > + function =3D "aon_cci"; > + drive-strength =3D <2>; > + bias-pull-up; > + }; > + }; > + > + cci1_sleep: cci1-sleep-state { > + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { > + /* cci_i2c_sda2, cci_i2c_scl2 */ > + pins =3D "gpio105", "gpio106"; > + function =3D "cci_i2c"; > + drive-strength =3D <2>; > + bias-pull-down; > + }; > + > + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { > + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ > + pins =3D "gpio235", "gpio236"; > + function =3D "aon_cci"; > + drive-strength =3D <2>; > + bias-pull-down; > + }; > + }; > + > edp0_hpd_default: edp0-hpd-default-state { > pins =3D "gpio119"; > function =3D "edp0_hot";