From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A15681DDC28; Mon, 16 Jun 2025 07:07:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750057631; cv=none; b=jlqxx9OUIckpb/Ui8kehS8/vO240/nuyIP0Nt6qz2naRXB3PrIDDizDC/V1SWHaMkkV2VzRWYg+26XQquzd77KkmQIOVXlq/IzSegLOoPhMB3FA+xwkxMn9aplVK2m1PJWVaTdYaz2IL8vntyWSO5xmVWXjZQGZEwwFFLtV99LA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750057631; c=relaxed/simple; bh=9+LWl9AzQ9yQ/TE1e5hn9Ex0bHyVkCirESj62LCSnmg=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=Cg1Vg8ZTVWugMnX/KjInD6ZYqY07+7TRANh4qATYMk0MoBOyvQJGBgAp3QIwduzePmKlqZ3DElUNprtRcbVMFb8sBvtWvxBbRSunSg40+oQwRWdv0wDXleV0Ygg7sfXS13CclYyW4RUse1+Oahlv8kF25CZtqHxJi0WjVO5W7Dg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BCrnaO3n; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BCrnaO3n" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DC8EAC4CEEA; Mon, 16 Jun 2025 07:07:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750057630; bh=9+LWl9AzQ9yQ/TE1e5hn9Ex0bHyVkCirESj62LCSnmg=; h=Date:Subject:To:References:From:In-Reply-To:From; b=BCrnaO3nhy9ADY+D1o0PZ4cQ4dj+1mpugBn1SDnDHQX0V7+jkzRQjH/wsJs+KSQOk Uk3q2ot7ziREnqdSu0HNTCCKUC/juVq0BzrmgAWPONrkcxRxd+JmdH8OYfUu9tsgZ/ XL4QLlstwVL9UGYqOdTAxuYzHUkj5rxMzdAautgo8xn5IX37BG5j17obR7xQAyZwOh rH9CM6aHyvA4n1QDz2wXMmjW0JkPuSMGSOL0+63BR2daDTKOdbIId4wCTCkHxcMKAg RM9hc5knd0/nV+tDNc0JJT11pqX/8uLSOelEwwhz65wpMNXYTuP3rQizN92SWGSuIg jm+7ABw/aRFyg== Message-ID: Date: Mon, 16 Jun 2025 09:07:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree To: Ryan Chen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , "nfraprado@collabora.com" , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" , "soc@lists.linux.dev" , Mo Elbadry , Rom Lemarchand , William Kennington , Yuxiao Zhang , "wthai@nvidia.com" , "leohu@nvidia.com" , "dkodihalli@nvidia.com" , "spuranik@nvidia.com" References: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> <20250612100933.3007673-4-ryan_chen@aspeedtech.com> <485749d4-b3c4-4965-9714-ad534d37e8c9@kernel.org> <749c581e-cc00-428f-8eb9-222f9d574486@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 16/06/2025 08:54, Ryan Chen wrote: >> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device >> tree >> >> On 16/06/2025 08:32, Ryan Chen wrote: >>>>> >>>>> But I don't know your previous "NAK, never tested" mean. >>>>> I did make CHECK_DTBS=y arch/arm64/boot/dts/aspeed/ don't see the >>>>> fail with >>>>> intc0: interrupt-controller@12100000 { >>>>> compatible = "simple-mfd"; >>>>> >>>>> So, could you point me more test instruction for this? >>>> See syscon.yaml. And writing bindings or talks on conferences: >>>> simple-mfd cannot be alone. >>>> >>> >>> intc0: interrupt-controller@12100000 { Sorry, do you mean add >>> by following? >>> compatible = "aspeed,intc-controller", "simple-mfd"; >>> ..... >>> intc0_11: interrupt-controller@1b00 { >>> compatible = "aspeed,ast2700-intc-ic"; >>> ...... >>> }; >>> }; >> >> Maybe, but you said this is base address, so how can it be some separate >> device? >> >> I mean really, don't add fake nodes just to satisfy some device instantiation. >> Describe what this really is. That is the job of DTS. Not some fake nodes. > > > Understood. Let me explain more about the hardware layout. > The interrupt controller space is decoded starting from 0x12100000, > which includes both a set of global configuration registers and > individual interrupt controller instances. > > The region at 0x12100000 contains global interrupt control registers > (e.g., protect config, interrupt routing etc.). This does not explain me why global controller registers are a BUS or MFD as you claimed here. > > The actual interrupt controller logic starts at 0x12101b00, where each sub-controller instance > (e.g., intc0_11, intc0_12, etc.) has its own set of registers. I don't know what is a "global controller register" and "own set of registers". If you have device spanning over multiple memory blocks, device takes multiple 'reg' entries for example. There are many other configurations, depending on real hardware and relationships. Just look at other DTS. Best regards, Krzysztof