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Fri, 20 Feb 2026 02:57:45 -0600 Received: from [10.24.50.20] (moteen-ubuntu-desk.dhcp.ti.com [10.24.50.20]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 61K8vgKD3594572; Fri, 20 Feb 2026 02:57:43 -0600 Message-ID: Date: Fri, 20 Feb 2026 14:27:41 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] arm64: dts: ti: k3-am62l-evm: Disable MMC0 internal pulls To: Judith Mendez , Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , , , , Andrew Davis References: <20260212184246.2316659-1-jm@ti.com> <20260212184246.2316659-3-jm@ti.com> Content-Language: en-US From: Moteen Shah In-Reply-To: <20260212184246.2316659-3-jm@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD5:EE_|PH0PR10MB997641:EE_ X-MS-Office365-Filtering-Correlation-Id: 010d3f8e-8e9d-4b4e-c3c3-08de705e1dfc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DQKasTidjyH6ejPFgifmhQLKvCDd3pzJXtsk/4HwlKiACorDbAPNagiuU5OY3Nk0rLXXh6z1ab2/l6cvIqw5kGNWsKPbEqHwtlFcARih+a0dvuHmNIcy8BnZQGtgHIM7FirHr8FNwhtLKESPGx/DoD7p0IPkdvcQgqlfCe/kVuiGx5UdsLm6Z+yQqAq/y9BV/h+YK+/4vYMRKRJfyb7DZ//ONzrXytQ6ovB+/gCyuY8BP/7nRJb0WGba5FOE9lCzS6zex8gheYFvlzVkbZjxo3lNvhq8YpT86utfaOfKGIjTApelii6iusElS7fC0AuGTzgC05AHo5ODYgRlLRmwND3BeGXBQAh3IL/W/eO3krL4/auGPHBEVutlFBl18Pb5Lfj098lx5tN+cEsGcd22I8XuGBfUkLRt1CkOS+aa/JeF/T0tush93Op1oNPD6qI8 X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Feb 2026 08:57:46.4605 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 010d3f8e-8e9d-4b4e-c3c3-08de705e1dfc X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR10MB997641 Hey Judith, On 13/02/26 00:12, Judith Mendez wrote: > AM62L EVM has external pullups on MMC0 CMD and D0 pins [0]. Remove > internal pullups considering: > - having both internal and external pullups reduces the total pull-up > resistance < 47K resulting in a value below the spec recommended 50K ohms > - having both pullups results in unnecessary power consumption > > Fixes: 00fb4c73b67d ("arm64: dts: ti: k3-am62l: add initial reference board file") > [0] https://www.ti.com/lit/zip/SPRCAL6 > Signed-off-by: Judith Mendez > --- > arch/arm64/boot/dts/ti/k3-am62l3-evm.dts | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts > index cae04cce33736..5085cd255fcd5 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts > +++ b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts > @@ -253,9 +253,9 @@ AM62LX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D8) I2C2_SDA */ > > mmc0_pins_default: mmc0-default-pins { > pinctrl-single,pins = < > - AM62LX_IOPAD(0x0214, PIN_INPUT_PULLUP, 0) /* (D2) MMC0_CMD */ > + AM62LX_IOPAD(0x0214, PIN_INPUT, 0) /* (D2) MMC0_CMD */ > AM62LX_IOPAD(0x020c, PIN_OUTPUT, 0) /* (B2) MMC0_CLK */ > - AM62LX_IOPAD(0x0208, PIN_INPUT_PULLUP, 0) /* (D3) MMC0_DAT0 */ > + AM62LX_IOPAD(0x0208, PIN_INPUT, 0) /* (D3) MMC0_DAT0 */ > AM62LX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (D4) MMC0_DAT1 */ > AM62LX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (C1) MMC0_DAT2 */ > AM62LX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (C2) MMC0_DAT3 */ Wont the change result in mismatched pullup resistance and will the mismatch between D0 and D1-D3 won't cause potential timing issues for modes with tighter timing requirements? Regards, Moteen