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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b4865e7e8d8sm1169370166b.41.2025.10.06.07.44.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Oct 2025 07:44:32 -0700 (PDT) Message-ID: Date: Mon, 6 Oct 2025 16:44:30 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] phy: qcom: qmp-combo: Move pipe_clk on/off to common To: Val Packett , Vinod Koul , Kishon Vijay Abraham I Cc: Dmitry Baryshkov , Neil Armstrong , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250927093915.45124-2-val@packett.cool> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250927093915.45124-2-val@packett.cool> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: GU5OUBUbRKTZcqveO1Oe6F3ExRNSRDmV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA0MDAyNyBTYWx0ZWRfX8X+AHnDCDL58 Py7qg/IA97TEgNBWLTQDt4fOtoOZ1VRjLywD1mQyGHW9NjyZKywtAAlKp4cdlC+5RS+WjaELMxM grHJT8BsTBz2QIfq1uj2u/NCFd1cqWeETJ7y2cctLfWUB+t8GfMMx+YJTZ9Dlz9nuI6FK+aeRVp FIXvO8XA4wkYtKXKh6L8QoJvlK4F2Qiilt8ovwqP/nIRY2SLKGzOWcPr2l+p4Qv7GMenOlLpDc5 LwVc9YVw3M41o9xjd8Bk+/EWoFYpV0GVGamwWG79PRw6NJItNGcaaGj6kwAEhvQYV6U5was54DN dVpY3/famQPrVljr6MhrrA9NWANdfw1Tf+3kKs2ggMYPbplQGy5850gfU9U1c+WtUcdXbAc9+H3 C1N6YzDSq1tFK9KhfeNpwFI6P6rk4g== X-Authority-Analysis: v=2.4 cv=Vqcuwu2n c=1 sm=1 tr=0 ts=68e3d5d4 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=N_By_h1aGXBmJSDtN4kA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-ORIG-GUID: GU5OUBUbRKTZcqveO1Oe6F3ExRNSRDmV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-06_04,2025-10-02_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 malwarescore=0 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2510040027 On 9/27/25 11:17 AM, Val Packett wrote: > Keep the USB pipe clock working when the phy is in DP-only mode, because > the dwc controller still needs it for USB 2.0 over the same Type-C port. > > Tested with the BenQ RD280UA monitor which has a downstream-facing port > for data passthrough that's manually switchable between USB 2 and 3, > corresponding to 4-lane and 2-lane DP respectively. > > Note: the suspend/resume callbacks were already gating the enable/disable > of this clock only on init_count and not usb_init_count! > > Signed-off-by: Val Packett > --- > o/ > > Just got my hands on a perfect test device for DP alt mode: a monitor with an > on-demand toggle between 2 and 4 lanes. (Started digging because I thought > I needed 4 lanes to use its full resolution and refresh rate, even though > it turned out to be the dpu adjusted mode clock check rejecting the modes, > patches for which are already posted.) > > In [1] Konrad mentioned that "the hardware disagrees" with keeping the USB > PLL always on. I'm not sure what exactly was meant by disagreement there, > and I didn't find any specific code that touches that PLL in the driver, > so I decided to just try it anyway. So what I did was playing around with the RESET_OVRD settings, which dictate what parts of the PHY (and their associated PLLs) are kept online.. but I totally forgot that there is a branch/gate clock in GCC that sits inbetween! > Before the changes, 4-lane mode would actually kill the USB 2.0 functionality > on the port, no recovery until reboot. > > With this patch, I can switch the monitor between 4-lane and 2-lane modes > (with an unplug-replug cycle..) and the USB 2.0 devices attached through > the monitor keep working! (I verified the number of lanes used via dp_debug). > > I'm sure it might not be that simple but from my limited and uninformed > understanding without any internal knowledge, the "sneaky workaround" > might actually be the intended way to do things? Normally the clock which you're enabling is sourced from the QMPPHY. The other option (bar some debug outputs) is for it to be driven by the 19.2 MHz always-on crystal (instead of $lots_of_mhz from the PHY). For USB hosts without a USB3 phy connected to them, there's an option to mux the controller's PIPE clock to be sourced from the UTMI clock input. In those cases, the UTMI (and therefore PIPE) clock runs at.. well, 19.2 MHz! (you can actually do that on USB3-phy-connected hosts too, at the cost of.. USB3, probably) So I'm not sure how much of that is well thought-out design and how much is luck, but this ends up working for us anyway, with seemingly no downsides. At least that's my understanding of the situation. > > Thanks, > ~val > > P.S. if I'm actually wrong and this is not acceptable for $reasons, the suspend > and resume callbacks would need to be changed to match the logic of having the > clk on depending on usb_init_count, not just the overall init_count. The suspend logic is broken and unused anyway, but that's a nice catch, the PIPE clock in question is even conveniently called "usb3_pipe" in DT > > [1]: https://lore.kernel.org/all/f21b7d52-4c3f-4e5b-bee7-f8b2945b5b02@oss.qualcomm.com/ > > --- > drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > index 7b5af30f1d02..c4bbd738eba1 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > @@ -3035,6 +3035,13 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) > if (ret) > goto err_assert_reset; > > + /* In DP-only mode, the pipe clk is still required for USB2 */ > + ret = clk_prepare_enable(qmp->pipe_clk); > + if (ret) { > + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); > + return ret; > + } > + > qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); > > /* override hardware control for reset of qmp phy */ > @@ -3103,6 +3110,7 @@ static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) > reset_control_bulk_assert(cfg->num_resets, qmp->resets); > > clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); > + clk_disable_unprepare(qmp->pipe_clk); Let's disable this one first, to preserve existing behavior (and it makes sense logically - if the PHY doesn't have its clocks, it can't really generate one either) Great job finding this! Konrad