From: Daniel Lezcano <daniel.lezcano@linaro.org>
To: aleksa.paunovic@htecgroup.com,
Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org,
Djordje Todorovic <djordje.todorovic@htecgroup.com>
Subject: Re: [PATCH RESEND v6 2/2] riscv: Allow for riscv-clock to pick up mmio address.
Date: Wed, 24 Sep 2025 15:45:42 +0200 [thread overview]
Message-ID: <e6a7cfe5-5443-4e10-981f-ca3811dadef8@linaro.org> (raw)
In-Reply-To: <20250924-riscv-time-mmio-v6-2-9c6158a14b37@htecgroup.com>
On 24/09/2025 13:10, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>
> Allow faster rdtime access via GCR.U mtime shadow register on RISC-V
> devices. This feature can be enabled by setting GCRU_TIME_MMIO
> during configuration.
> Reformat the clint timer to use the same mechanism if RISCV_M_MODE is set.
>
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
Thanks for resending but I was waiting for a tag from the maintainers.
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next prev parent reply other threads:[~2025-09-24 13:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-24 11:10 [PATCH RESEND v6 0/2] riscv: Use GCR.U timer device as clocksource Aleksa Paunovic via B4 Relay
2025-09-24 11:10 ` [PATCH RESEND v6 1/2] dt-bindings: timer: mips,p8700-gcru Aleksa Paunovic via B4 Relay
2025-09-24 11:10 ` [PATCH RESEND v6 2/2] riscv: Allow for riscv-clock to pick up mmio address Aleksa Paunovic via B4 Relay
2025-09-24 13:45 ` Daniel Lezcano [this message]
2025-09-24 15:35 ` Vivian Wang
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