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Wed, 27 Aug 2025 22:13:15 +0000 Message-ID: Date: Wed, 27 Aug 2025 15:13:12 -0700 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next] net: stmmac: sun8i: drop unneeded default syscon value To: Andre Przywara , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , "Alexandre Torgue" CC: Chen-Yu Tsai , Samuel Holland , "Jernej Skrabec" , Corentin LABBE , Paul Kocialkowski , , , References: <20250825172055.19794-1-andre.przywara@arm.com> Content-Language: en-US From: Jacob Keller Autocrypt: addr=jacob.e.keller@intel.com; keydata= xjMEaFx9ShYJKwYBBAHaRw8BAQdAE+TQsi9s60VNWijGeBIKU6hsXLwMt/JY9ni1wnsVd7nN J0phY29iIEtlbGxlciA8amFjb2IuZS5rZWxsZXJAaW50ZWwuY29tPsKTBBMWCgA7FiEEIEBU qdczkFYq7EMeapZdPm8PKOgFAmhcfUoCGwMFCwkIBwICIgIGFQoJCAsCBBYCAwECHgcCF4AA CgkQapZdPm8PKOiZAAEA4UV0uM2PhFAw+tlK81gP+fgRqBVYlhmMyroXadv0lH4BAIf4jLxI UPEL4+zzp4ekaw8IyFz+mRMUBaS2l+cpoBUBzjgEaFx9ShIKKwYBBAGXVQEFAQEHQF386lYe MPZBiQHGXwjbBWS5OMBems5rgajcBMKc4W4aAwEIB8J4BBgWCgAgFiEEIEBUqdczkFYq7EMe apZdPm8PKOgFAmhcfUoCGwwACgkQapZdPm8PKOjbUQD+MsPBANqBUiNt+7w0dC73R6UcQzbg cFx4Yvms6cJjeD4BAKf193xbq7W3T7r9BdfTw6HRFYDiHXgkyoc/2Q4/T+8H In-Reply-To: <20250825172055.19794-1-andre.przywara@arm.com> Content-Type: multipart/signed; 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boundary="------------2phpSMfOdv9bZhHJID9Gxv4D"; protected-headers="v1" From: Jacob Keller To: Andre Przywara , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue Cc: Chen-Yu Tsai , Samuel Holland , Jernej Skrabec , Corentin LABBE , Paul Kocialkowski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Message-ID: Subject: Re: [PATCH net-next] net: stmmac: sun8i: drop unneeded default syscon value References: <20250825172055.19794-1-andre.przywara@arm.com> In-Reply-To: <20250825172055.19794-1-andre.przywara@arm.com> --------------2phpSMfOdv9bZhHJID9Gxv4D Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 8/25/2025 10:20 AM, Andre Przywara wrote: > For some odd reason we were very jealous about the value of the EMAC > clock register from the syscon block, insisting on a reset value and > only doing read-modify-write operations on that register, even though w= e > pretty much know the register layout. > This already led to a basically redundant entry for the H6, which only > differs by that value. We seem to have the same situation with the new > A523 SoC, which again is compatible to the A64, but has a different > syscon reset value. >=20 > Drop any assumptions about that value, and set or clear the bits that w= e > want to program, from scratch (starting with a value of 0). For the > remove() implementation, we just turn on the POWERDOWN bit, and deselec= t > the internal PHY, which mimics the existing code. >=20 > Signed-off-by: Andre Przywara > Reviewed-by: Jernej Skrabec > Acked-by: Corentin LABBE > Tested-by: Corentin LABBE > Tested-by: Paul Kocialkowski > Reviewed-by: Paul Kocialkowski > --- > Hi, >=20 > this follows up on my RFC post from April[1]. We figured that the old > approach (insisting on a certain reset value) was never really needed, = and > some people tested this on various hardware, many thanks for that! >=20 > No real changes except solving one conflict after rebasing on top of > v6.17-rc1, and adding the tags from the diligent reviewers! >=20 > Cheers, > Andre >=20 Makes sense. Its simpler to build up from 0 instead of trying to build up from the current baseline with a warning that was unnecessary. Reviewed-by: Jacob Keller > [1] https://lore.kernel.org/netdev/20250423095222.1517507-1-andre.przyw= ara@arm.com/ >=20 > .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 47 ++-----------------= > 1 file changed, 4 insertions(+), 43 deletions(-) >=20 > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/driver= s/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > index 2796dc426943e..690f3650f84ed 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > @@ -31,10 +31,6 @@ > */ > =20 > /* struct emac_variant - Describe dwmac-sun8i hardware variant > - * @default_syscon_value: The default value of the EMAC register in sy= scon > - * This value is used for disabling properly EMAC > - * and used as a good starting value in case of the > - * boot process(uboot) leave some stuff. > * @syscon_field reg_field for the syscon's gmac register > * @soc_has_internal_phy: Does the MAC embed an internal PHY > * @support_mii: Does the MAC handle MII > @@ -48,7 +44,6 @@ > * value of zero indicates this is not supported. > */ > struct emac_variant { > - u32 default_syscon_value; > const struct reg_field *syscon_field; > bool soc_has_internal_phy; > bool support_mii; > @@ -94,7 +89,6 @@ static const struct reg_field sun8i_ccu_reg_field =3D= { > }; > =20 > static const struct emac_variant emac_variant_h3 =3D { > - .default_syscon_value =3D 0x58000, > .syscon_field =3D &sun8i_syscon_reg_field, > .soc_has_internal_phy =3D true, > .support_mii =3D true, > @@ -105,14 +99,12 @@ static const struct emac_variant emac_variant_h3 =3D= { > }; > =20 > static const struct emac_variant emac_variant_v3s =3D { > - .default_syscon_value =3D 0x38000, > .syscon_field =3D &sun8i_syscon_reg_field, > .soc_has_internal_phy =3D true, > .support_mii =3D true > }; > =20 > static const struct emac_variant emac_variant_a83t =3D { > - .default_syscon_value =3D 0, > .syscon_field =3D &sun8i_syscon_reg_field, > .soc_has_internal_phy =3D false, > .support_mii =3D true, > @@ -122,7 +114,6 @@ static const struct emac_variant emac_variant_a83t = =3D { > }; > =20 > static const struct emac_variant emac_variant_r40 =3D { > - .default_syscon_value =3D 0, > .syscon_field =3D &sun8i_ccu_reg_field, > .support_mii =3D true, > .support_rgmii =3D true, > @@ -130,7 +121,6 @@ static const struct emac_variant emac_variant_r40 =3D= { > }; > =20 > static const struct emac_variant emac_variant_a64 =3D { > - .default_syscon_value =3D 0, > .syscon_field =3D &sun8i_syscon_reg_field, > .soc_has_internal_phy =3D false, > .support_mii =3D true, > @@ -141,7 +131,6 @@ static const struct emac_variant emac_variant_a64 =3D= { > }; > =20 > static const struct emac_variant emac_variant_h6 =3D { > - .default_syscon_value =3D 0x50000, > .syscon_field =3D &sun8i_syscon_reg_field, > /* The "Internal PHY" of H6 is not on the die. It's on the > * co-packaged AC200 chip instead. > @@ -933,25 +922,11 @@ static int sun8i_dwmac_set_syscon(struct device *= dev, > struct sunxi_priv_data *gmac =3D plat->bsp_priv; > struct device_node *node =3D dev->of_node; > int ret; > - u32 reg, val; > - > - ret =3D regmap_field_read(gmac->regmap_field, &val); > - if (ret) { > - dev_err(dev, "Fail to read from regmap field.\n"); > - return ret; > - } > - > - reg =3D gmac->variant->default_syscon_value; > - if (reg !=3D val) > - dev_warn(dev, > - "Current syscon value is not the default %x (expect %x)\n", > - val, reg); > + u32 reg =3D 0, val; Ok, here is where you used to read the value and log a warning if it was different from the expected?> > if (gmac->variant->soc_has_internal_phy) { > if (of_property_read_bool(node, "allwinner,leds-active-low")) > reg |=3D H3_EPHY_LED_POL; > - else > - reg &=3D ~H3_EPHY_LED_POL; > =20 > /* Force EPHY xtal frequency to 24MHz. */ > reg |=3D H3_EPHY_CLK_SEL; > @@ -965,11 +940,6 @@ static int sun8i_dwmac_set_syscon(struct device *d= ev, > * address. No need to mask it again. > */ > reg |=3D ret << H3_EPHY_ADDR_SHIFT; > - } else { > - /* For SoCs without internal PHY the PHY selection bit should be > - * set to 0 (external PHY). > - */ > - reg &=3D ~H3_EPHY_SELECT; You used to clear this value here for SoC without internal PHY. This is ok to remove since you are building up from zero so this is already clear by default. > } > =20 > if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { > @@ -980,8 +950,6 @@ static int sun8i_dwmac_set_syscon(struct device *de= v, > val /=3D 100; > dev_dbg(dev, "set tx-delay to %x\n", val); > if (val <=3D gmac->variant->tx_delay_max) { > - reg &=3D ~(gmac->variant->tx_delay_max << > - SYSCON_ETXDC_SHIFT); > reg |=3D (val << SYSCON_ETXDC_SHIFT); > } else { > dev_err(dev, "Invalid TX clock delay: %d\n", > @@ -998,8 +966,6 @@ static int sun8i_dwmac_set_syscon(struct device *de= v, > val /=3D 100; > dev_dbg(dev, "set rx-delay to %x\n", val); > if (val <=3D gmac->variant->rx_delay_max) { > - reg &=3D ~(gmac->variant->rx_delay_max << > - SYSCON_ERXDC_SHIFT); > reg |=3D (val << SYSCON_ERXDC_SHIFT); > } else { > dev_err(dev, "Invalid RX clock delay: %d\n", > @@ -1008,11 +974,6 @@ static int sun8i_dwmac_set_syscon(struct device *= dev, > } > } > =20 > - /* Clear interface mode bits */ > - reg &=3D ~(SYSCON_ETCS_MASK | SYSCON_EPIT); > - if (gmac->variant->support_rmii) > - reg &=3D ~SYSCON_RMII_EN; > - > switch (plat->mac_interface) { > case PHY_INTERFACE_MODE_MII: > /* default */ > @@ -1039,9 +1000,9 @@ static int sun8i_dwmac_set_syscon(struct device *= dev, > =20 > static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) > { > - u32 reg =3D gmac->variant->default_syscon_value; > - > - regmap_field_write(gmac->regmap_field, reg); > + if (gmac->variant->soc_has_internal_phy) > + regmap_field_write(gmac->regmap_field, > + (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)); But now instead, you set it only if you *do* have an internal PHY. Good. > } > =20 > static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)= --------------2phpSMfOdv9bZhHJID9Gxv4D-- --------------WjBELPf3F7uabgmB8y6VMZz3 Content-Type: application/pgp-signature; name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wnsEABYIACMWIQQgQFSp1zOQVirsQx5qll0+bw8o6AUCaK+C+QUDAAAAAAAKCRBqll0+bw8o6HhO AQDNTwKxbdFOO3HBR7ov+DTnw/uXnyjNqaaVWFaJuQOiOQEAzhxewYt9mzSuZAttEbHzGcz5YxJI uu3YHjKL8lP7rA4= =O0VR -----END PGP SIGNATURE----- --------------WjBELPf3F7uabgmB8y6VMZz3--