From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.mindbit.ro (xs1.mindbit.ro [80.86.107.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9A072D5C83 for ; Sun, 16 Aug 2026 15:28:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.86.107.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786894096; cv=none; b=pZjvLd4nPe6nwsUDcr/KRsKyf71ZaDTQeh8uZGrJE+Vm4Fg0WOJ3HrXmyK6tamG8vTZUUI2kYYoybTTJWlTn5sbWohdnKsGNgWel1nMxL/0g+b9h7OxRqiNqgmLcwq6Nlo8Y7UTIlCbWAq3uH+XymwuKU7iKvDBMnmCXHzm6kQw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786894096; c=relaxed/simple; bh=mT67PHljh+uS0aVy8eCOCnXaSflMHLvaR3Z9yRLRuwA=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=s4Sned2n62PBbP+I+dc579bMLzUuqq2FIs7Rzywr7MBcBXa0uBVNW7zk8xb51zDlwWfkmcusG748O91+iThNLQt5jzEV8Llek75ktBSlz5wd93mD2k8NapH7Y7NPxs+MQ5NT+CkxrfzaxqA6ZI+1RppQ0fIa4qb4B4aRZF3kPJk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=rendec.net; spf=pass smtp.mailfrom=rendec.net; dkim=pass (2048-bit key) header.d=rendec.net header.i=@rendec.net header.b=uewTgXmh; arc=none smtp.client-ip=80.86.107.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=rendec.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rendec.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rendec.net header.i=@rendec.net header.b="uewTgXmh" Received: from dog.kanata.rendec.net (pool-174-112-193-187.cpe.net.cable.rogers.com [174.112.193.187]) by mail.mindbit.ro (Postfix) with ESMTPSA id 37D02CC6BB; Sun, 16 Aug 2026 18:28:10 +0300 (EEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.mindbit.ro 37D02CC6BB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rendec.net; s=default; t=1786894092; bh=7OOVJe7QtwNsFabdXE48VCdNc7uTbafySFa80JTrPPg=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=uewTgXmhUWaeiVFp9z2bWTcWaeE1XYj66thKuh8LSCqYGALkAdL2nkCHhxyNQsk6u GNmDK7U3jIwW8O/QYp22VvVra7eM/hG3vEdshB4WMnwj6EBg5vEdRszA9zHHnb2lXF 9QSKf8bXD48xEMnmpSq+aXBafGYeGZcvZTjXDbTZFZMlJJJVn0cEPPbxtCvE0RaMN1 u+dguHrrNNhZJ5QEFShYE9a+OCs5gHzf53HrpKV1kv7wZma8082OlG0PGsZ0SqIH0J G95R3+PRAwz4x/mI8u3MGDZ2Mb3zdu7HkJQsmidB8d2pBQ4TZjAQzhV8JiZ3pXFvHn 6je4l/c5QnvZg== Message-ID: Subject: Re: [PATCH 5/5] irqchip/imsic: Use IPI_MAX instead of IMSIC_NR_IPI From: Radu Rendec To: Guo Ren , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: palmer@dabbelt.com, pjw@kernel.org, aou@eecs.berkeley.edu, alex@ghiti.fr, tglx@kernel.org, daniel.lezcano@kernel.org, anup@brainfault.org, hui.wang@canonical.com, samuel.holland@sifive.com Date: Sun, 16 Aug 2026 11:28:08 -0400 In-Reply-To: <20260816070049.2097442-6-guoren@kernel.org> References: <20260816070049.2097442-1-guoren@kernel.org> <20260816070049.2097442-6-guoren@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.3 (3.58.3-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Sun, 2026-08-16 at 07:00 +0000, Guo Ren wrote: > From: "GUO Ren (XuanTie)" >=20 > IMSIC was defining its own IMSIC_NR_IPI (=3D 8) which happened to match > the architecture's IPI_MAX. Now that IPI_MAX is exported from riscv > asm/smp.h, use the architecture constant and drop the private define. >=20 > This keeps the number of multiplexed IPIs in sync with the rest of the > RISC-V IPI infrastructure. >=20 > Signed-off-by: GUO Ren (XuanTie) > --- > =C2=A0drivers/irqchip/irq-riscv-imsic-early.c | 4 ++-- > =C2=A0drivers/irqchip/irq-riscv-imsic-state.h | 1 - > =C2=A02 files changed, 2 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/ir= q-riscv-imsic-early.c > index 12efd241ce88..823f5f2ecb3d 100644 > --- a/drivers/irqchip/irq-riscv-imsic-early.c > +++ b/drivers/irqchip/irq-riscv-imsic-early.c > @@ -67,12 +67,12 @@ static int __init imsic_ipi_domain_init(void) > =C2=A0 return 0; > =C2=A0 > =C2=A0 /* Create IMSIC IPI multiplexing */ > - virq =3D ipi_mux_create(IMSIC_NR_IPI, imsic_ipi_send); > + virq =3D ipi_mux_create(IPI_MAX, imsic_ipi_send); > =C2=A0 if (virq <=3D 0) > =C2=A0 return virq < 0 ? virq : -ENOMEM; > =C2=A0 > =C2=A0 /* Set vIRQ range */ > - riscv_ipi_set_virq_range(virq, IMSIC_NR_IPI); > + riscv_ipi_set_virq_range(virq, IPI_MAX); > =C2=A0 > =C2=A0 /* Announce that IMSIC is providing IPIs */ > =C2=A0 pr_info("%pfwP: providing IPIs using interrupt %d\n", imsic->fwnod= e, IMSIC_IPI_ID); > diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/ir= q-riscv-imsic-state.h > index c42ee180b305..878cc192ccec 100644 > --- a/drivers/irqchip/irq-riscv-imsic-state.h > +++ b/drivers/irqchip/irq-riscv-imsic-state.h > @@ -13,7 +13,6 @@ > =C2=A0#include > =C2=A0 > =C2=A0#define IMSIC_IPI_ID 1 > -#define IMSIC_NR_IPI 8 > =C2=A0 > =C2=A0struct imsic_vector { > =C2=A0 /* Fixed details of the vector */ Reviewed-by: Radu Rendec