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[84.157.75.208]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b61ca48c40sm10159988f8f.58.2025.07.21.03.44.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Jul 2025 03:44:27 -0700 (PDT) Message-ID: Date: Mon, 21 Jul 2025 12:44:26 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/7] nvmem: qcom-spmi-sdam: Migrate to devm_spmi_subdevice_alloc_and_add() Content-Language: en-US To: AngeloGioacchino Del Regno , sboyd@kernel.org Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org References: <20250721075525.29636-1-angelogioacchino.delregno@collabora.com> <20250721075525.29636-3-angelogioacchino.delregno@collabora.com> From: Casey Connolly In-Reply-To: <20250721075525.29636-3-angelogioacchino.delregno@collabora.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Angelo, On 21/07/2025 09:55, AngeloGioacchino Del Regno wrote: > Some Qualcomm PMICs integrate a SDAM device, internally located in > a specific address range reachable through SPMI communication. > > Instead of using the parent SPMI device (the main PMIC) as a kind > of syscon in this driver, register a new SPMI sub-device for SDAM > and initialize its own regmap with this sub-device's specific base > address, retrieved from the devicetree. > > This allows to stop manually adding the register base address to > every R/W call in this driver, as this can be, and is now, handled > by the regmap API instead. This is honestly a really nice improvement :D> > Signed-off-by: AngeloGioacchino Del Regno > --- > drivers/nvmem/qcom-spmi-sdam.c | 41 +++++++++++++++++++++++++--------- > 1 file changed, 30 insertions(+), 11 deletions(-) > > diff --git a/drivers/nvmem/qcom-spmi-sdam.c b/drivers/nvmem/qcom-spmi-sdam.c > index 4f1cca6eab71..1b80e8563a33 100644 > --- a/drivers/nvmem/qcom-spmi-sdam.c > +++ b/drivers/nvmem/qcom-spmi-sdam.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > > #define SDAM_MEM_START 0x40 > #define REGISTER_MAP_ID 0x40 > @@ -20,7 +21,6 @@ > struct sdam_chip { > struct regmap *regmap; > struct nvmem_config sdam_config; > - unsigned int base; > unsigned int size; > }; > > @@ -73,7 +73,7 @@ static int sdam_read(void *priv, unsigned int offset, void *val, > return -EINVAL; > } > > - rc = regmap_bulk_read(sdam->regmap, sdam->base + offset, val, bytes); > + rc = regmap_bulk_read(sdam->regmap, offset, val, bytes); > if (rc < 0) > dev_err(dev, "Failed to read SDAM offset %#x len=%zd, rc=%d\n", > offset, bytes, rc); > @@ -100,7 +100,7 @@ static int sdam_write(void *priv, unsigned int offset, void *val, > return -EINVAL; > } > > - rc = regmap_bulk_write(sdam->regmap, sdam->base + offset, val, bytes); > + rc = regmap_bulk_write(sdam->regmap, offset, val, bytes); > if (rc < 0) > dev_err(dev, "Failed to write SDAM offset %#x len=%zd, rc=%d\n", > offset, bytes, rc); > @@ -110,28 +110,47 @@ static int sdam_write(void *priv, unsigned int offset, void *val, > > static int sdam_probe(struct platform_device *pdev) > { > + struct regmap_config sdam_regmap_config = { > + .reg_bits = 16, > + .val_bits = 16, I believe registers are 8 bits wide, at least on Qualcomm platforms. Kind regards, -- // Casey (she/her)