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X-CSE-ConnectionGUID: /GM8inDWTMuHvj7DRy79ng== X-CSE-MsgGUID: DaTE+ZnUSsO//O4LdEDRjA== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="9018534" X-IronPort-AV: E=Sophos;i="6.07,209,1708416000"; d="scan'208";a="9018534" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2024 06:18:44 -0700 X-CSE-ConnectionGUID: sMzf6z22SD618eNgS1KsNw== X-CSE-MsgGUID: FJFoLFuUSRyFr4MWccoxdg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,209,1708416000"; d="scan'208";a="23211608" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.35]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2024 06:18:41 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Wed, 17 Apr 2024 16:18:37 +0300 (EEST) To: Shravan Kumar Ramani cc: Hans de Goede , Vadim Pasternak , David Thompson , platform-driver-x86@vger.kernel.org, LKML Subject: Re: [PATCH v1 2/3] platform/mellanox: mlxbf-pmc: Add support for 64-bit counters and cycle count In-Reply-To: Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Wed, 17 Apr 2024, Shravan Kumar Ramani wrote: > Add support for programming any counter to monitor the cycle count. > Since counting of cycles using 32-bit ocunters would result in frequent > wraparounds, add the ability to combine 2 adjacent 32-bit counters to > form 1 64-bit counter. > Both these features are supported by BlueField-3 PMC hardware, hence > the required bit-fields are exposed by the driver via sysfs to allow > the user to configure as needed. > > Signed-off-by: Shravan Kumar Ramani > Reviewed-by: David Thompson > Reviewed-by: Vadim Pasternak > --- > @@ -1799,6 +1902,37 @@ static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned int blk_ > attr = NULL; > } > > + if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE) { > + /* > + * Couple adjacent odd and even 32-bit counters to form 64-bit counters > + * using "use_odd_counter" sysfs which has one bit per even counter. > + */ > + attr = &pmc->block[blk_num].attr_use_odd_counter; > + attr->dev_attr.attr.mode = 0644; > + attr->dev_attr.show = mlxbf_pmc_use_odd_counter_show; > + attr->dev_attr.store = mlxbf_pmc_use_odd_counter_store; > + attr->nr = blk_num; > + attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL, > + "use_odd_counter"); > + if (!attr->dev_attr.attr.name) > + return -ENOMEM; > + pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr; > + attr = NULL; > + > + /* Program crspace counters to count clock cycles using "count_clock" sysfs */ > + attr = &pmc->block[blk_num].attr_count_clock; > + attr->dev_attr.attr.mode = 0644; > + attr->dev_attr.show = mlxbf_pmc_count_clock_show; > + attr->dev_attr.store = mlxbf_pmc_count_clock_store; > + attr->nr = blk_num; > + attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL, > + "count_clock"); > + if (!attr->dev_attr.attr.name) > + return -ENOMEM; > + pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr; > + attr = NULL; > + } Hi, What was the reason why this driver could not use .dev_groups to setup sysfs (filtering can be done with .is_visible)? -- i.