From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C62BC352AA for ; Tue, 1 Oct 2019 12:33:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 63F6221924 for ; Tue, 1 Oct 2019 12:33:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387872AbfJAMdv (ORCPT ); Tue, 1 Oct 2019 08:33:51 -0400 Received: from mga12.intel.com ([192.55.52.136]:21857 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726181AbfJAMdu (ORCPT ); Tue, 1 Oct 2019 08:33:50 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Oct 2019 05:33:50 -0700 X-IronPort-AV: E=Sophos;i="5.64,571,1559545200"; d="scan'208";a="185168539" Received: from likexu-mobl1.ccr.corp.intel.com (HELO [10.249.172.165]) ([10.249.172.165]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/AES256-SHA; 01 Oct 2019 05:33:46 -0700 Subject: Re: [PATCH 3/3] KVM: x86/vPMU: Add lazy mechanism to release perf_event per vPMC To: Peter Zijlstra Cc: Paolo Bonzini , kvm@vger.kernel.org, rkrcmar@redhat.com, sean.j.christopherson@intel.com, vkuznets@redhat.com, Jim Mattson , Ingo Molnar , Arnaldo Carvalho de Melo , ak@linux.intel.com, wei.w.wang@intel.com, kan.liang@intel.com, like.xu@intel.com, ehankland@google.com, arbel.moshe@oracle.com, linux-kernel@vger.kernel.org References: <20190930072257.43352-1-like.xu@linux.intel.com> <20190930072257.43352-4-like.xu@linux.intel.com> <20191001082321.GL4519@hirez.programming.kicks-ass.net> From: Like Xu Organization: Intel OTC Message-ID: Date: Tue, 1 Oct 2019 20:33:45 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191001082321.GL4519@hirez.programming.kicks-ass.net> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Peter, On 2019/10/1 16:23, Peter Zijlstra wrote: > On Mon, Sep 30, 2019 at 03:22:57PM +0800, Like Xu wrote: >> + union { >> + u8 event_count :7; /* the total number of created perf_events */ >> + bool enable_cleanup :1; > > That's atrocious, don't ever create a bitfield with base _Bool. I saw this kind of usages in the tree such as "struct arm_smmu_master/tipc_mon_state/regmap_irq_chip". I'm not sure is this your personal preference or is there a technical reason such as this usage is not incompatible with union syntax? My design point is to save a little bit space without introducing two variables such as "int event_count & bool enable_cleanup". One of the alternatives is to introduce "u8 pmu_state", where the last seven bits are event_count for X86_PMC_IDX_MAX and the highest bit is the enable_cleanup bit. Are you OK with this ? By the way, is the lazy release mechanism looks reasonable to you? > >> + } state; >