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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FX2IHTM6QrVsNgD3K1VlBm1cpQyTm/pvN8T0+EfXBgr3aFCFPcv6L32D8oPf3NG6Iw447LuwVQdeaBekEO3NFm8yrdIZ9Y8yhw2n4b7H2p9g4B+xP/vJmIaiW/lOUpOanmQwssBiSDUZNCRCQBQya0aQdO24Yj6ExN4aYnLpE9AtG95EX/rRKbcYf0OQ0RpGFAWrsae/M3zzB2f1eC/Z40qxHd/S5CganygvEhOeAptgTCeXXsrIh6aheAb2uaPYON00oiZx0p2+x3qjpDVny1z44bDN/J1V+uH8QE0IPMH6HXkwmAtxuJYtDwP+Q4hKjydYelhWZgOyh+A2nAunl4W70DM/+on9oA2Z+8Gvm/3wI5zEsFhewsroKTCYLAEx2yCGVfhJPCfxFRn+vkhhDcb/QjLD+nFDXMgb63HwsIjywYpm+DCBqBmDpF1NEU1k X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Mar 2026 11:34:28.9534 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b8770a0-d53a-44f8-906b-08de8bf4cec0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F41.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPFAF883AE17 Hello Andrea, On 3/27/2026 3:14 PM, Andrea Righi wrote: > Hi Vincent, > > On Fri, Mar 27, 2026 at 09:45:56AM +0100, Vincent Guittot wrote: >> On Thu, 26 Mar 2026 at 16:12, Andrea Righi wrote: >>> >>> When choosing which idle housekeeping CPU runs the idle load balancer, >>> prefer one on a fully idle core if SMT is active, so balance can migrate >>> work onto a CPU that still offers full effective capacity. Fall back to >>> any idle candidate if none qualify. >> >> This one isn't straightforward for me. The ilb cpu will check all >> other idle CPUs 1st and finish with itself so unless the next CPU in >> the idle_cpus_mask is a sibling, this should not make a difference >> >> Did you see any perf diff ? > > I actually see a benefit, in particular, with the first patch applied I see > a ~1.76x speedup, if I add this on top I get ~1.9x speedup vs baseline, > which seems pretty consistent across runs (definitely not in error range). > > The intention with this change was to minimize SMT noise running the ILB > code on a fully-idle core when possible, but I also didn't expect to see > such big difference. > > I'll investigate more to better understand what's happening. Interesting! Either this "CPU-intensive workload" hates SMT turning busy (but to an extent where performance drops visibly?) or ILB keeps getting interrupted on an SMT sibling that is burdened by interrupts leading to slower balance (or IRQs driving the workload being delayed by rq_lock disabling them) Would it be possible to share the total SCHED_SOFTIRQ time, load balancing attempts, and utlization with and without the patch? I too will go queue up some runs to see if this makes a difference. -- Thanks and Regards, Prateek