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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45e037b9215sm55951445e9.12.2025.09.12.02.20.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 Sep 2025 02:20:27 -0700 (PDT) Message-ID: Date: Fri, 12 Sep 2025 10:20:24 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] arm64: dts: qcom: x1e80100: Add IRIS video codec To: Stephan Gerhold , Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dikshita Agarwal , Vikash Garodia , Neil Armstrong References: <20250911-x1e-iris-dt-v1-0-63caf0fd202c@linaro.org> <20250911-x1e-iris-dt-v1-1-63caf0fd202c@linaro.org> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <20250911-x1e-iris-dt-v1-1-63caf0fd202c@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/09/2025 19:38, Stephan Gerhold wrote: > Add the IRIS video codec to accelerate video decoding/encoding. Copied > mostly from sm8550.dtsi, only the opp-table is slightly different for X1E. > For opp-240000000, we need to vote for a higher OPP on one of the power > domains, because the voltage requirements for the PLL and the derived > clocks differ (sm8550.dtsi has the same). > > Signed-off-by: Stephan Gerhold > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 87 ++++++++++++++++++++++++++++++++++ > 1 file changed, 87 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index ba602eddfb54616ad38205570bc56a1f0e62c023..d6914165d055cd0c0e80541267e2671c7432799e 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -5234,6 +5234,93 @@ usb_1_ss1_dwc3_ss: endpoint { > }; > }; > > + iris: video-codec@aa00000 { > + compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris"; > + > + reg = <0 0x0aa00000 0 0xf0000>; > + interrupts = ; > + > + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, > + <&videocc VIDEO_CC_MVS0_GDSC>, > + <&rpmhpd RPMHPD_MXC>, > + <&rpmhpd RPMHPD_MMCX>; > + power-domain-names = "venus", > + "vcodec0", > + "mxc", > + "mmcx"; > + operating-points-v2 = <&iris_opp_table>; > + > + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, > + <&videocc VIDEO_CC_MVS0C_CLK>, > + <&videocc VIDEO_CC_MVS0_CLK>; > + clock-names = "iface", > + "core", > + "vcodec0_core"; > + > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "cpu-cfg", > + "video-mem"; > + > + memory-region = <&video_mem>; > + > + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; > + reset-names = "bus"; > + > + iommus = <&apps_smmu 0x1940 0>, > + <&apps_smmu 0x1947 0>; > + dma-coherent; > + > + /* > + * IRIS firmware is signed by vendors, only > + * enable in boards where the proper signed firmware > + * is available. > + */ > + status = "disabled"; > + > + iris_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-192000000 { > + opp-hz = /bits/ 64 <192000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>, > + <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-240000000 { > + opp-hz = /bits/ 64 <240000000>; > + required-opps = <&rpmhpd_opp_svs>, > + <&rpmhpd_opp_low_svs>; > + }; > + > + opp-338000000 { > + opp-hz = /bits/ 64 <338000000>; > + required-opps = <&rpmhpd_opp_svs>, > + <&rpmhpd_opp_svs>; > + }; > + > + opp-366000000 { > + opp-hz = /bits/ 64 <366000000>; > + required-opps = <&rpmhpd_opp_svs_l1>, > + <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-444000000 { > + opp-hz = /bits/ 64 <444000000>; > + required-opps = <&rpmhpd_opp_nom>, > + <&rpmhpd_opp_nom>; > + }; > + > + opp-481000000 { > + opp-hz = /bits/ 64 <481000000>; > + required-opps = <&rpmhpd_opp_turbo>, > + <&rpmhpd_opp_turbo>; > + }; > + }; > + }; > + > videocc: clock-controller@aaf0000 { > compatible = "qcom,x1e80100-videocc"; > reg = <0 0x0aaf0000 0 0x10000>; > Assuming /in/s//on/ Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue # x1e Inspiron 14p