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[93.144.65.248]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493c6375764sm314379715e9.5.2026.07.06.02.35.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2026 02:35:06 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 14/15] arm64: dts: imx8mn-var-som-symphony: enable PWM1 Date: Mon, 6 Jul 2026 11:34:44 +0200 Message-ID: X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Stefano Radaelli Enable PWM1 on the Symphony carrier board and add the corresponding pinctrl configuration. Signed-off-by: Stefano Radaelli --- v1->v2: - .../boot/dts/freescale/imx8mn-var-som-symphony.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index ddd4651b35d7..2afb5b438b68 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -217,6 +217,12 @@ &i2c4 { status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + /* Header */ &uart1 { pinctrl-names = "default"; @@ -310,6 +316,12 @@ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x06 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 -- 2.47.3