From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752411AbdJ0Oxh (ORCPT ); Fri, 27 Oct 2017 10:53:37 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:37499 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751278AbdJ0Oxe (ORCPT ); Fri, 27 Oct 2017 10:53:34 -0400 From: Philippe CORNU To: Rob Herring CC: Arnd Bergmann , Russell King , "Mark Rutland" , Archit Taneja , Andrzej Hajda , Laurent Pinchart , David Airlie , "Philipp Zabel" , Benjamin Gaignard , Bhumika Goyal , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , Yannick FERTRE , Vincent ABRIOU , Alexandre TORGUE , Maxime Coquelin , Gabriel FERNANDEZ , Ludovic BARRE , Fabien DESSENNE , "Mickael REULIER" Subject: Re: [PATCH] dt-bindings: display: stm32: add pixel clock mandatory property Thread-Topic: [PATCH] dt-bindings: display: stm32: add pixel clock mandatory property Thread-Index: AQHTTzE4Q7OtGnMGZUibN/DeWRiXy6L3pniA Date: Fri, 27 Oct 2017 14:52:21 +0000 Message-ID: References: <1509034356-23885-1-git-send-email-philippe.cornu@st.com> <20171027143815.evbb7rqkgqiol7yo@rob-hp-laptop> In-Reply-To: <20171027143815.evbb7rqkgqiol7yo@rob-hp-laptop> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.50] Content-Type: text/plain; charset="utf-8" Content-ID: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-10-27_08:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id v9RErfPa008729 Hi Rob, On 10/27/2017 04:38 PM, Rob Herring wrote: > On Thu, Oct 26, 2017 at 06:12:36PM +0200, Philippe Cornu wrote: >> Add the DPI/RGB input pixel clock in mandatory properties >> because it really offers a better preciseness for timing >> computations. >> Note: Fix also the DSI panel example where "ref" & "pclk" >> clocks were swapped. >> >> Signed-off-by: Philippe Cornu >> --- >> Documentation/devicetree/bindings/display/st,stm32-ltdc.txt | 6 ++++-- >> 1 file changed, 4 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt >> index 0292522..99823fb 100644 >> --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt >> +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt >> @@ -28,6 +28,7 @@ Mandatory properties specific to STM32 DSI: >> - #size-cells: Should be <0>. >> - compatible: "st,stm32-dsi". >> - clock-names: >> + - DPI/RGB input pixel clock string name, must be "px_clk". >> - phy pll reference clock string name, must be "ref". > > Where's pclk? pclk is described in the generic part (Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt) as mandatory. In st,stm32-ltdc.txt (specific part), I have documented that "For all mandatory properties & nodes, please refer to the related documentation in [5]". Do you think it is clear enough? > > The new clock should be last to be backwards compatible. > ok. Many thanks for your review and your support, Philippe :-) >> - resets: see [5]. >> - reset-names: see [5]. >> @@ -97,8 +98,9 @@ Example 2: DSI panel >> #size-cells = <0>; >> compatible = "st,stm32-dsi"; >> reg = <0x40016c00 0x800>; >> - clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; >> - clock-names = "ref", "pclk"; >> + clocks = <&rcc 1 CLK_F469_DSI>, <&rcc 1 CLK_LCD>, >> + <&clk_hse>; >> + clock-names = "pclk", "px_clk", "ref"; >> resets = <&rcc STM32F4_APB2_RESET(DSI)>; >> reset-names = "apb"; >> >> -- >> 1.9.1 >>