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According to the > AMD APM,any pages corresponding to MMIO addresses must be configured > with the C-bit clear. > > The current *_iommu_set_prot() implementation sets the C-bit on all PTEs > in the IOMMU page tables. This is incorrect for PTEs backed by MMIO, and > can break PCIe peer-to-peer communication when IOVA is used. Fix this by > avoiding the C-bit for MMIO-backed mappings. > > For amdv2 IOMMU page tables, there is a usage scenario for GVA->GPA > mappings, and for the trusted MMIO in the TEE-IO case, the C-bit will need > to be added to GPA. However, SNP guests do not yet support vIOMMU, and the > trusted MMIO support is not ready in upstream. Adding the C-bit for trusted > MMIO can be considered once those features land. > > Fixes: 879ced2bab1b ("iommupt: Add the AMD IOMMU v1 page table format") > Fixes: aef5de756ea8 ("iommupt: Add the x86 64 bit page table format") > Suggested-by: Jason Gunthorpe > Signed-off-by: Wei Wang > Reviewed-by: Jason Gunthorpe > Reviewed-by: Kevin Tian Reviewed-by: Vasant Hegde -Vasant