From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m3298.qiye.163.com (mail-m3298.qiye.163.com [220.197.32.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7479D3EBF1A for ; Wed, 11 Feb 2026 14:30:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.98 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770820210; cv=none; b=fRddAZshOmbSuzwDX17Fc7pR6IXqkxfjslnT10SWavpXQ1PwjSnVuZ2ZcYwHAMtRNr29bxKccnfsHQzijoX3bI4vTEW6KREf77AK8y0+5RSSx2I47pBKCaF4KC3B0m7c2LxXdfPRTQbivzvrhKlzvJJScJMUVlcD5ExGe0i1LEI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770820210; c=relaxed/simple; bh=Z0h/IFZxTUAY2VxqjpyIO+QHV29yU+s5JcYzwXiJn0o=; h=Cc:Subject:To:References:From:Message-ID:Date:MIME-Version: In-Reply-To:Content-Type; b=ZxGFkVdW5Zv7S+STEOOhXzDgLJ02TjfpjCPB4W4rOvTfXM6NUYxuNr1qrqlw9hNrt1tOqPF+ifX3zFdmpTehBk+EYSRXTFb2SSkmI8kHc3Cojhy6VEpVFr1NYFNQYfULWQ1B8DUbV8qARp7zSCH8z9YzS6dwUM78UvusnC2AQzE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=XXEaKLkW; arc=none smtp.client-ip=220.197.32.98 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="XXEaKLkW" Received: from [172.16.12.14] (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 33e12f735; Wed, 11 Feb 2026 22:24:51 +0800 (GMT+08:00) Cc: shawn.lin@rock-chips.com, quentin.schulz@cherry.de, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: Re: [PATCH v2 2/4] arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-tiger To: Heiko Stuebner References: <20260210080303.680403-1-heiko@sntech.de> <20260210080303.680403-3-heiko@sntech.de> From: Shawn Lin Message-ID: Date: Wed, 11 Feb 2026 22:24:49 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: <20260210080303.680403-3-heiko@sntech.de> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit X-HM-Tid: 0a9c4d172f9709cckunm937070351137e9 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQxlCS1ZPHksdS0pJSElOTElWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=XXEaKLkWVXFuigclxFWuBXetqB9jU7Iis9D+Z2ZK2gvCJLZCcyAcRUZoH4jIvMhWqEzslLTkTVkWBdU8HuJHHg+8Y3No4gustF4ZZY/bWMoSnz+GcSPg1ItD0/sQWj8cSv3K1CK7V9j4vuLGzAE9lE9HrVSG5aH7RIlNV1AIIz0=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=1cbYuRDQwymK6OOU58iBAkyi1AjdH/qPbmtobJhA14U=; h=date:mime-version:subject:message-id:from; ÔÚ 2026/02/10 ÐÇÆÚ¶þ 16:03, Heiko Stuebner дµÀ: > From: Heiko Stuebner > > Using a combination of fixed clock and gpio-gate clock works but does > not describe the actual hardware. Use the gated-fixed-clock binding > to describe this in a nicer way. > > Signed-off-by: Heiko Stuebner > --- > .../arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 19 +++++-------------- > 1 file changed, 5 insertions(+), 14 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi > index 27269b7b08aa..b4b8f305935f 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi > @@ -47,23 +47,14 @@ led-1 { > }; > }; > > - /* > - * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE > - * clock generator. > - * The clock output is gated via the OE pin on the clock generator. > - * This is modeled as a fixed-clock plus a gpio-gate-clock. > - */ > - pcie_refclk_gen: pcie-refclk-gen-clock { > - compatible = "fixed-clock"; > + /* 100MHz PCIe reference clock from PI6C557-05BLE */ > + pcie_refclk: pcie-clock-generator { > + compatible = "gated-fixed-clock"; > #clock-cells = <0>; > clock-frequency = <100000000>; > - }; > - > - pcie_refclk: pcie-refclk-clock { > - compatible = "gpio-gate-clock"; > - clocks = <&pcie_refclk_gen>; > - #clock-cells = <0>; > + clock-output-names = "pcie-refclk-clock"; > enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */ The change itself looks fine , so Reviewed-by: Shawn Lin However, if it's designed as active high, I would say Tiger is against the the PCIe spec about how L1 substate work. Perhaps you could check PCIe spec v7.0, Figure 5-16 Example: L1.2 Waveforms Illustrating Upstream Port Initiated Exit.. When in L1.2, clkreq# should be released by both ends, and the pull-up register by whatevery way will make it into high, and thus refclk is gated automatically. > + vdd-supply = <&vcca_3v3_s0>; > }; > > vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { >