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Tue, 02 Jun 2026 07:29:42 -0700 (PDT) Received: from intellaptop.lan ([2607:fea8:fc01:88aa:f1de:f35:7935:804f]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7e695d8a609sm10083330a34.24.2026.06.02.07.29.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 07:29:42 -0700 (PDT) Message-ID: Subject: Re: [PATCH 22/28] KVM: x86/mmu: introduce cpu_role bit for availability of PFEC.I/D From: mlevitsk@redhat.com To: Paolo Bonzini , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: d.riley@proxmox.com, jon@nutanix.com Date: Tue, 02 Jun 2026 10:29:41 -0400 In-Reply-To: <20260505195226.563317-23-pbonzini@redhat.com> References: <20260505195226.563317-1-pbonzini@redhat.com> <20260505195226.563317-23-pbonzini@redhat.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-2.fc40) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2026-05-05 at 21:52 +0200, Paolo Bonzini wrote: > While GMET looks a lot like SMEP, it has several annoying differences. > The main one is that the availability of the I/D bit in the page fault > error code still depends on the host CR4.SMEP and EFER.NXE bits.=C2=A0 If= the Hi! What do you think if we reword this like this: "still depends on either host's CR4.SMEP or host's EFER.NXE being set" I initially thought that we have to have both of these settings enabled and= it confused me. > base.cr4_smep bit of the cpu_role is (ab)used to enable GMET, there needs > to be another place where the host CR4.SMEP is read from; just merge it > with EFER.NXE into a new cpu_role bit that tells paging_tmpl.h whether > to set the I/D bit at all. I am thinking: For KVM point of view, has_pferr_fetch will always be true on NPT, because = the kernel itself always enables EFER.NX, if it can (for reference, the code is in head_64.S), and there seems to be = no override for that. And then, KVM refuses to load when EFER.NX is not supported by the CPU=C2= =A0 So host's EFER.NX will always be set for KVM (we can add an assert somewher= e to be 100% sure) In fact if this is the case, we can simplifiy things by assuming that we al= ways have PFERR_FETCH for NPT. What do you think? >=20 > Tested-by: David Riley > Signed-off-by: Paolo Bonzini > --- > =C2=A0arch/x86/include/asm/kvm_host.h | 7 +++++++ > =C2=A0arch/x86/kvm/mmu/mmu.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 | 8 ++++++++ > =C2=A0arch/x86/kvm/mmu/paging_tmpl.h=C2=A0 | 2 +- > =C2=A03 files changed, 16 insertions(+), 1 deletion(-) >=20 > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_h= ost.h > index 23a7ac8d7fbe..7dde4ca87752 100644 > --- a/arch/x86/include/asm/kvm_host.h > +++ b/arch/x86/include/asm/kvm_host.h > @@ -414,6 +414,13 @@ union kvm_mmu_extended_role { > =C2=A0 unsigned int cr4_smap:1; > =C2=A0 unsigned int cr4_la57:1; > =C2=A0 unsigned int efer_lma:1; > + > + /* > + * True if either CR4.SMEP or EFER.NXE are set.=C2=A0 For AMD NPT > + * this is the "real" host CR4.SMEP whereas cr4_smep is > + * actually GMET. > + */ If we adopt my suggestion of using 'role.has_user_exec_permission', then I guess we won't need this patch? What do you think?=20 Side question: Is it true that CR4.SMEP *on the host* is not needed for NPT= /GMET? (I wasn't able to find anything in the manual) Best regards, Maxim Levitsky > + unsigned int has_pferr_fetch:1; > =C2=A0 }; > =C2=A0}; > =C2=A0 > diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c > index 156bab8afbc6..912c8e97ef61 100644 > --- a/arch/x86/kvm/mmu/mmu.c > +++ b/arch/x86/kvm/mmu/mmu.c > @@ -234,6 +234,11 @@ BUILD_MMU_ROLE_ACCESSOR(ext,=C2=A0 cr4, la57); > =C2=A0BUILD_MMU_ROLE_ACCESSOR(base, efer, nx); > =C2=A0BUILD_MMU_ROLE_ACCESSOR(ext,=C2=A0 efer, lma); > =C2=A0 > +static inline bool has_pferr_fetch(struct kvm_mmu *mmu) > +{ > + return mmu->cpu_role.ext.has_pferr_fetch; > +} > + > =C2=A0static inline bool is_cr0_pg(struct kvm_mmu *mmu) > =C2=A0{ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return mmu->cpu_role.bas= e.level > 0; > @@ -5793,6 +5798,8 @@ static union kvm_cpu_role kvm_calc_cpu_role(struct = kvm_vcpu *vcpu, > =C2=A0 role.ext.cr4_pke =3D ____is_efer_lma(regs) && ____is_cr4_pke(regs)= ; > =C2=A0 role.ext.cr4_la57 =3D ____is_efer_lma(regs) && ____is_cr4_la57(reg= s); > =C2=A0 role.ext.efer_lma =3D ____is_efer_lma(regs); > + > + role.ext.has_pferr_fetch =3D role.base.efer_nx | role.base.cr4_smep; > =C2=A0 return role; > =C2=A0} > =C2=A0 > @@ -5946,6 +5953,7 @@ void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu,= unsigned long cr0, > =C2=A0 > =C2=A0 /* NPT requires CR0.PG=3D1. */ > =C2=A0 WARN_ON_ONCE(cpu_role.base.direct || !cpu_role.base.guest_mode); > + cpu_role.base.cr4_smep =3D false; > =C2=A0 > =C2=A0 root_role =3D cpu_role.base; > =C2=A0 root_role.level =3D kvm_mmu_get_tdp_level(vcpu); > diff --git a/arch/x86/kvm/mmu/paging_tmpl.h b/arch/x86/kvm/mmu/paging_tmp= l.h > index 047400af924d..07100bbfc270 100644 > --- a/arch/x86/kvm/mmu/paging_tmpl.h > +++ b/arch/x86/kvm/mmu/paging_tmpl.h > @@ -489,7 +489,7 @@ static int FNAME(walk_addr_generic)(struct guest_walk= er *walker, > =C2=A0 > =C2=A0error: > =C2=A0 errcode |=3D write_fault | user_fault; > - if (fetch_fault && (is_efer_nx(mmu) || is_cr4_smep(mmu))) > + if (fetch_fault && has_pferr_fetch(mmu)) > =C2=A0 errcode |=3D PFERR_FETCH_MASK; > =C2=A0 > =C2=A0 walker->fault.vector =3D PF_VECTOR;