From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A15CC25B6B for ; Thu, 26 Oct 2023 02:57:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233017AbjJZC50 (ORCPT ); Wed, 25 Oct 2023 22:57:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231337AbjJZC5Y (ORCPT ); Wed, 25 Oct 2023 22:57:24 -0400 Received: from out30-97.freemail.mail.aliyun.com (out30-97.freemail.mail.aliyun.com [115.124.30.97]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF0E3194; Wed, 25 Oct 2023 19:57:18 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R191e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046049;MF=baolin.wang@linux.alibaba.com;NM=1;PH=DS;RN=10;SR=0;TI=SMTPD_---0Vuw6fix_1698289034; Received: from 30.97.48.63(mailfrom:baolin.wang@linux.alibaba.com fp:SMTPD_---0Vuw6fix_1698289034) by smtp.aliyun-inc.com; Thu, 26 Oct 2023 10:57:15 +0800 Message-ID: Date: Thu, 26 Oct 2023 10:57:30 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values To: xu lh Cc: Linhua Xu , Linus Walleij , Orson Zhai , Chunyan Zhang , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Andy Shevchenko , Zhirong Qiu , Xiongpeng Wu References: <20230908055146.18347-1-Linhua.xu@unisoc.com> <20230908055146.18347-6-Linhua.xu@unisoc.com> From: Baolin Wang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/25/2023 7:29 PM, xu lh wrote: > On Tue, Sep 12, 2023 at 4:37 PM Baolin Wang > wrote: > >> >> >> On 9/8/2023 1:51 PM, Linhua Xu wrote: >>> From: Linhua Xu >>> >>> As the UNISOC pin controller version iterates, more registers are >> required >>> to meet new functional requirements. Thus modify them. >>> >>> Signed-off-by: Linhua Xu >>> --- >>> drivers/pinctrl/sprd/pinctrl-sprd.h | 30 +++++++++++++++-------------- >>> 1 file changed, 16 insertions(+), 14 deletions(-) >>> >>> diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h >> b/drivers/pinctrl/sprd/pinctrl-sprd.h >>> index a696f81ce663..5357874186fd 100644 >>> --- a/drivers/pinctrl/sprd/pinctrl-sprd.h >>> +++ b/drivers/pinctrl/sprd/pinctrl-sprd.h >>> @@ -7,30 +7,32 @@ >>> #ifndef __PINCTRL_SPRD_H__ >>> #define __PINCTRL_SPRD_H__ >>> >>> +#include >>> + >>> struct platform_device; >>> >>> -#define NUM_OFFSET (20) >>> -#define TYPE_OFFSET (16) >>> -#define BIT_OFFSET (8) >>> -#define WIDTH_OFFSET (4) >>> +#define NUM_OFFSET 22 >>> +#define TYPE_OFFSET 18 >>> +#define BIT_OFFSET 10 >>> +#define WIDTH_OFFSET 6 >>> >>> #define SPRD_PIN_INFO(num, type, offset, width, reg) \ >>> - (((num) & 0xFFF) << NUM_OFFSET | \ >>> - ((type) & 0xF) << TYPE_OFFSET | \ >>> - ((offset) & 0xFF) << BIT_OFFSET | \ >>> - ((width) & 0xF) << WIDTH_OFFSET | \ >>> - ((reg) & 0xF)) >>> + (((num) & GENMASK(10, 0)) << NUM_OFFSET | \ >>> + ((type) & GENMASK(3, 0)) << TYPE_OFFSET | \ >>> + ((offset) & GENMASK(7, 0)) << BIT_OFFSET | \ >>> + ((width) & GENMASK(3, 0)) << WIDTH_OFFSET | \ >>> + ((reg) & GENMASK(5, 0))) >> >> Can you define some readable macro for the mask bits? > > >>> okay. Do you think the following modification is okay? > +#define PIN_ID GENMASK(10, 0) > +#define PIN_TYPE GENMASK(3, 0) > +#define FIELD_OFFSET GENMASK(7, 0) > +#define FIELD_WIDTH GENMASK(3, 0) > +#define PIN_REG GENMASK(5, 0) Looks better. To keep consistent, I perfer to something as below: #define NUM_MASK xxx #define TYPE_MASK xxx #define BIT_MASK xxx #define WIDTH_MASK xxx #define REG_MASK xxx