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charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: CHcm7HR4Q2kEKTqk3yaQrsrVeUnOLnL8 X-Proofpoint-ORIG-GUID: CHcm7HR4Q2kEKTqk3yaQrsrVeUnOLnL8 X-Authority-Analysis: v=2.4 cv=baZrUPPB c=1 sm=1 tr=0 ts=6816c89c cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=UqCG9HQmAAAA:8 a=tOIPKxuczE_Drth-FjcA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA0MDAxNiBTYWx0ZWRfX5wXFbgM+eOI3 cwh9nyqDvI6HiK19DVcVeBwfZmB8CeB2MW5LZiXTEydWR6Zc+Oh3oF9Ok8zxTVHDHOR3KAGFvlU iAHf+o26QisVbUn94A8K2S2ApIxK19iAB4IsIgBpzM0deb4l5Zz9qCOHNcc/pgqIWuxvxpIgMSM eyi/ZVgH2Jf1ImacZYBTNxv6QQ1kDxaFaPh3tlTqfm8DQiU7mIoZXAD/nHYj0oSpnY/XiXx4ykP FOGqDnuvMWYulKz+tusLDlnlVCXO0Q9BF/NLqO7YWzHwZgQLXAAYJue5dNiNeDZ9XvjSzIjh4F0 2KlG5ltHcy1Ti8DBHi6cfcgKioxGchyYjNyo3ljRFkMDAyHToScvioK/J1B27nA0cM5+CdyEZZZ mHLabjUwhnehQtix584jmKfMfWylsPFTAR21SpgIsONixX/Nk19uYnznAz3A5tgHftct4VUm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-04_01,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 impostorscore=0 bulkscore=0 phishscore=0 mlxlogscore=612 clxscore=1015 suspectscore=0 spamscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505040016 On 5/2/2025 6:15 PM, George Moussalem via B4 Relay wrote: > From: George Moussalem > > Add CMN PLL node for enabling output clocks to the networking > hardware blocks on IPQ5018 devices. > > The reference clock of CMN PLL is routed from XO to the CMN PLL > through the internal WiFi block. > .XO (96 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL. The clock tree: .XO (48 MHZ)-->WiFi (multiplier/divider)--> 96 MHZ to CMN PLL.