From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C0E5C7112F for ; Fri, 18 Aug 2023 07:16:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358140AbjHRHQa (ORCPT ); Fri, 18 Aug 2023 03:16:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358135AbjHRHP5 (ORCPT ); Fri, 18 Aug 2023 03:15:57 -0400 Received: from mail.3ffe.de (0001.3ffe.de [159.69.201.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3EA030DF for ; Fri, 18 Aug 2023 00:15:55 -0700 (PDT) Received: from 3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 83A02957; Fri, 18 Aug 2023 09:15:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1692342953; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Be1l9jlqDSr/+Vna3fROrPkK+Sce6tQqng+uemlZghY=; b=rH0DK2crq7R5+CGkVPumDVriL8K/DDyC54D3vIkceS50ytbr0635qyMrW+/YG1EHKmqSJD 3cQugFqvvN52MjSJ6mPmE01yIsscLXSvbaQcBdr2QEVNAfwwnyF6eTl9bTPpHHpjQN6xSl G5FPy3PXbt0WUJrnOwLZT5tpgvaIfZIAEpx71tBWri2tqCRm4SOk3K0oODFyLN5sS7BAU1 0SO8CVuJcDXsK1pyzZfbIR/81rWKyYn1kVMhgUv0pYfbCWrwUyBxPPINtbOzxlwUxsP6+i TiaaWS6jyLyMb/h2AaFLBi1PCm1WB3klbbrfVdblIJHMsGxoigLBfoaDc1lpOw== MIME-Version: 1.0 Date: Fri, 18 Aug 2023 09:15:53 +0200 From: Michael Walle To: Hsin-Yi Wang Cc: Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] mtd: spi-nor: Check bus width while setting QE bit In-Reply-To: <20230818064524.1229100-2-hsinyi@chromium.org> References: <20230818064524.1229100-2-hsinyi@chromium.org> Message-ID: X-Sender: michael@walle.cc Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > spi_nor_write_16bit_sr_and_check() should also check if bus width is > 4 before setting QE bit. > > Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on > lock()/unlock()") > Suggested-by: Michael Walle > Suggested-by: Tudor Ambarus > Signed-off-by: Hsin-Yi Wang I'm not sure if the comment beneath needs an update, too. In any case: Reviewed-by: Michael Walle > --- > v2: > https://lore.kernel.org/lkml/20230816104245.2676965-1-hsinyi@chromium.org/ > --- > drivers/mtd/spi-nor/core.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index 614960c7d22cc..1328128dfe65c 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -870,7 +870,9 @@ static int spi_nor_write_16bit_sr_and_check(struct > spi_nor *nor, u8 sr1) > ret = spi_nor_read_cr(nor, &sr_cr[1]); > if (ret) > return ret; > - } else if (nor->params->quad_enable) { > + } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 && > + spi_nor_get_protocol_width(nor->write_proto) == 4 && > + nor->params->quad_enable) { > /* > * If the Status Register 2 Read command (35h) is not > * supported, we should at least be sure we don't