From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABA01C433EF for ; Tue, 12 Jul 2022 06:49:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232102AbiGLGtu (ORCPT ); Tue, 12 Jul 2022 02:49:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229709AbiGLGts (ORCPT ); Tue, 12 Jul 2022 02:49:48 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EC331EEFF; Mon, 11 Jul 2022 23:49:40 -0700 (PDT) X-UUID: 2c5deefdde4d4c63a28299ad0b6e2f3a-20220712 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:88eb9b1a-e6b5-4e14-9a7a-0762369b27a7,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:45 X-CID-INFO: VERSION:1.1.8,REQID:88eb9b1a-e6b5-4e14-9a7a-0762369b27a7,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTIO N:release,TS:45 X-CID-META: VersionHash:0f94e32,CLOUDID:27f90b64-0b3f-4b2c-b3a6-ed5c044366a0,C OID:9a67550cb39b,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 2c5deefdde4d4c63a28299ad0b6e2f3a-20220712 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1513253721; Tue, 12 Jul 2022 14:49:37 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 12 Jul 2022 14:49:36 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 12 Jul 2022 14:49:35 +0800 Message-ID: Subject: Re: [PATCH v13 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort driver From: Rex-BC Chen To: CK Hu , "chunkuang.hu@kernel.org" , "p.zabel@pengutronix.de" , "daniel@ffwll.ch" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "mripard@kernel.org" , "tzimmermann@suse.de" , "matthias.bgg@gmail.com" , "deller@gmx.de" , "airlied@linux.ie" CC: "msp@baylibre.com" , "granquet@baylibre.com" , Jitao Shi =?UTF-8?Q?=28=E7=9F=B3=E8=AE=B0=E6=B6=9B=29?= , "wenst@chromium.org" , "angelogioacchino.delregno@collabora.com" , LiangXu Xu =?UTF-8?Q?=28=E5=BE=90=E4=BA=AE=29?= , "dri-devel@lists.freedesktop.org" , "linux-mediatek@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-fbdev@vger.kernel.org" , Project_Global_Chrome_Upstream_Group Date: Tue, 12 Jul 2022 14:49:35 +0800 In-Reply-To: <7af5710c5a9c0c30e38ca81a72fe30c1c7749bbb.camel@mediatek.com> References: <20220701062808.18596-1-rex-bc.chen@mediatek.com> <20220701062808.18596-6-rex-bc.chen@mediatek.com> <7af5710c5a9c0c30e38ca81a72fe30c1c7749bbb.camel@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2022-07-07 at 16:00 +0800, CK Hu wrote: > Hi, Bo-Chen: > > On Fri, 2022-07-01 at 14:28 +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann > > > > This patch adds a embedded displayport driver for the MediaTek > > mt8195 > > SoC. > > > > It supports the MT8195, the embedded DisplayPort units. It offers > > DisplayPort 1.4 with up to 4 lanes. > > > > The driver creates a child device for the phy. The child device > > will > > never exist without the parent being active. As they are sharing a > > register range, the parent passes a regmap pointer to the child so > > that > > both can work with the same register range. The phy driver sets > > device > > data that is read by the parent to get the phy device that can be > > used > > to control the phy properties. > > > > This driver is based on an initial version by > > Jitao shi > > > > Signed-off-by: Markus Schneider-Pargmann > > Signed-off-by: Guillaume Ranquet > > Signed-off-by: Bo-Chen Chen > > --- > > [snip] > > > + > > +static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp, > > + enum dp_pixelformat color_format) > > +{ > > + u32 val; > > + > > + /* update MISC0 */ > > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034, > > + color_format << DP_TEST_COLOR_FORMAT_SHIFT, > > + DP_TEST_COLOR_FORMAT_MASK); > > + > > + switch (color_format) { > > + case DP_PIXELFORMAT_YUV422: > > + val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422; > > + break; > > + case DP_PIXELFORMAT_RGB: > > + val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB; > > + break; > > + default: > > The default case would never happen, remove it. > > Regards, > CK > Hello CK, after removing default, it will build error because we do not handle other 5 enum in enum dp_pixelformat. "error: 5 enumeration values not handled in switch" Therefore, I will keep this. BRs, Bo-Chen > > + drm_warn(mtk_dp->drm_dev, "Unsupported color format: > > %d\n", > > + color_format); > > + return -EINVAL; > > + } > > + > > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C, > > + val, PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK); > > + return 0; > > +} > > + > >