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Wed, 29 Apr 2026 23:45:17 -0700 (PDT) X-Received: by 2002:a05:6a20:a120:b0:3a2:d79c:4161 with SMTP id adf61e73a8af0-3a3cf86fe19mr1867919637.47.1777531517182; Wed, 29 Apr 2026 23:45:17 -0700 (PDT) Received: from [10.217.198.242] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-834ed5ccb1fsm4173594b3a.17.2026.04.29.23.45.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Apr 2026 23:45:16 -0700 (PDT) Message-ID: Date: Thu, 30 Apr 2026 12:15:12 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] pinctrl: qcom: Unconditionally mark gpio as wakeup enable To: Sneh Mankad , Bjorn Andersson , Linus Walleij , Neil Armstrong , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20260430-enable_wakeup_capable_gpios-v1-1-5de39bf06094@oss.qualcomm.com> Content-Language: en-US From: "Maulik Shah (mkshah)" In-Reply-To: <20260430-enable_wakeup_capable_gpios-v1-1-5de39bf06094@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: zALv1B8MRCUOrLDTktwLVrMCCBekz5Ft X-Proofpoint-ORIG-GUID: zALv1B8MRCUOrLDTktwLVrMCCBekz5Ft X-Authority-Analysis: v=2.4 cv=DPy/JSNb c=1 sm=1 tr=0 ts=69f2fa7e cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=gK-aurLV-Wj7dvaEeU8A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDMwMDA2NCBTYWx0ZWRfX7TaKKiQl2jlC mlz/FlcYgahQetX7PlwY9VdLjwkwZNCoclMEr/eyKUcoBx90DzdTZstcmpW0XRmVqtQ4m4HwocS oNcIDvxvlXS6gVcibKsBmhwJqTsupJIwnRaTOb6bZ9B5dc3Jc5zTkqIwiqPT9AobtzZu0Neknw+ 3MsVJRzFFlzmGg2JbHa7SXNAhBVAEEMm3jNBXvaGTKHz+CPVjkbEPI0IDutBii2hNC86NMZppPq mSS6r8amIZQrL3DYLYrG19cx4d3m/vkCafWao/h8xra8rX6QKBFbzVfK6kje3Oz1Q6ADkHAHIuS qxUgbiQ3L3oAp7ONSPa5jbP0wUqmH8pwANWf92clPHgci8gcH14rXihdmgDwmLcXvhsqGc4c2Y6 b3m5l8+xsL1NwTzMcEZIEN5vuzFRusn3oUGvGpVuFiv1U+H2dUqhsu+ok2QGZpQYJ0QzJPi41eO h/RYnnLnAFrfXrI3lBg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-30_02,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604300064 On 4/30/2026 11:24 AM, Sneh Mankad wrote: > The wakeup enable bit needs to be set irrespective of the SoC using PDC or > MPM as wakeup capable irqchip to allow the GPIO interrupts to be forwarded > to parent irqchip. > > This is set only for PDC irqchip using additional check skip_wake_irqs > making it impossible for MPM irqchip to detect the GPIO interrupt during > SoC low power mode since for MPM irqchip the skip_wake_irqs is always > false. > > Remove skip_wake_irqs condition when setting wakeup enable bit to allow > forwarding GPIO interrupts for SoCs using MPM irqchip too. > > Fixes: 76b446f5b86e ("pinctrl: qcom: handle intr_target_reg wakeup_present/enable bits") > Signed-off-by: Sneh Mankad > --- > drivers/pinctrl/qcom/pinctrl-msm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c > index 45b3a2763eb85405fecdd4770ba3d4ab684563f0..96df8eb8f5d3f3bcfe165ac02a07414e491f1178 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.c > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c > @@ -1247,7 +1247,7 @@ static int msm_gpio_irq_reqres(struct irq_data *d) > * While the name implies only the wakeup event, it's also required for > * the interrupt event. > */ Pasting full comment from driver, since this is not visible in the diff. /* * If the wakeup_enable bit is present and marked as available for the * requested GPIO, it should be enabled when the GPIO is marked as * wake irq in order to allow the interrupt event to be transfered to * the PDC HW. * While the name implies only the wakeup event, it's also required for * the interrupt event. */ Can you update in the above comment also to mention both PDC and MPM HW. While touching this comment, please also correct spelling typo for transfered. "transferred to the PDC/MPM HW." Post this update, Reviewed-by: Maulik Shah Thanks, Maulik > - if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { > + if (g->intr_wakeup_present_bit) { > u32 intr_cfg; > > raw_spin_lock_irqsave(&pctrl->lock, flags); > @@ -1275,7 +1275,7 @@ static void msm_gpio_irq_relres(struct irq_data *d) > unsigned long flags; > > /* Disable the wakeup_enable bit if it has been set in msm_gpio_irq_reqres() */ > - if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { > + if (g->intr_wakeup_present_bit) { > u32 intr_cfg; > > raw_spin_lock_irqsave(&pctrl->lock, flags); > > --- > base-commit: b4e07588e743c989499ca24d49e752c074924a9a > change-id: 20260430-enable_wakeup_capable_gpios-cb9439ae8772 > > Best regards,