From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E73531578E for ; Fri, 17 Jul 2026 07:09:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784272155; cv=none; b=oCvkmkBCc+EF7FJusUipGN3CgDJMuLaR3EHdpk+lLq2xdbI2j/FHDpQkqmQwVt0f7TC/s14CrchDNCvLLHix8V6+UUsl1ErUI7d04oZ4qXNFTH30/tDfH8lEHmXBHQlq1ILetNmDrblvfwS/Ovk5n2SKqqHQfk52In9lj+DM0kM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784272155; c=relaxed/simple; bh=6mjGUns3fQ+yk/shjL4Fk/icFOmerwZPVUag0qFztAA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:From:In-Reply-To: Content-Type:References; b=SnKA8tvFXBKMzyC/2/Cfq3tTBMKMEMDKZugnXLi2D2IO/PCLB9qEeGjj172ECUtcBopDygtl9B9VLSyZaE3KgKVirrEzqvGkluTUdYTnfpd/+gB2CznkqAP0wvGEZDSSMDwOD3cPmWwTS8MvQTu7oxGDyM+NlHo9kr3Sme1QfSQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=dFNvDmfx; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="dFNvDmfx" Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20260717070901euoutp02620a95d40f48c4076a3e7709195fd662~DAg8ijULp2168921689euoutp02J for ; Fri, 17 Jul 2026 07:09:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20260717070901euoutp02620a95d40f48c4076a3e7709195fd662~DAg8ijULp2168921689euoutp02J DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1784272141; bh=gtEtKbHALVeV7/efubUhmI22PqwCe1yhJ2IyP3FSt9s=; h=Date:Subject:To:Cc:From:In-Reply-To:References:From; b=dFNvDmfxv0mnhYWD/TC39+402DpGxFvRupb40s2iL+jKJrE60qSGOdVmSsOj0UHC5 W+D3kHfjMwNOx/SmiQvCO5r8/ASO2nTaScH4zQWMQZ4h9HzUQgd5ZvCdu+kp2Nj+Zz CdhbIp614/XxRHvVfXWJISnTCqmRQP60rOGfx4qE= Received: from eusmtip2.samsung.com (unknown [203.254.199.222]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20260717070900eucas1p11e7d4abd6e0c32fa18fca2940cdcca70~DAg8Byc9i1966119661eucas1p1c; Fri, 17 Jul 2026 07:09:00 +0000 (GMT) Received: from [106.210.134.192] (unknown [106.210.134.192]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20260717070900eusmtip2f3c550cb45bbd547ca91cf756f839bd9~DAg7fSehb0082300823eusmtip2S; Fri, 17 Jul 2026 07:09:00 +0000 (GMT) Message-ID: Date: Fri, 17 Jul 2026 09:08:59 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Betterbird (Windows) Subject: Re: [PATCH v2 2/3] riscv: mm: Apply Svinval in update_mmu_cache() To: Klara Modin , Xu Lu Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com Content-Language: en-US From: Marek Szyprowski In-Reply-To: Content-Transfer-Encoding: 8bit X-CMS-MailID: 20260717070900eucas1p11e7d4abd6e0c32fa18fca2940cdcca70 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260717070900eucas1p11e7d4abd6e0c32fa18fca2940cdcca70 X-EPHeader: CA X-CMS-RootMailID: 20260717070900eucas1p11e7d4abd6e0c32fa18fca2940cdcca70 References: <20260715132009.10634-1-luxu.kernel@bytedance.com> <20260715132009.10634-3-luxu.kernel@bytedance.com> On 15.07.2026 20:22, Klara Modin wrote: > On 2026-07-15 21:20:08 +0800, Xu Lu wrote: >> Use Svinval in update_mmu_cache_range() when the extension is available. >> >> Signed-off-by: Xu Lu > This version works fine for me. Lucky You! Here BPiF3 gets frozen once userspace has started. > Thanks, > Tested-by: Klara Modin > >> --- >> arch/riscv/include/asm/pgtable.h | 8 ++++++++ >> arch/riscv/include/asm/tlbflush.h | 18 ++++++++++++++++++ >> arch/riscv/mm/tlbflush.c | 18 ------------------ >> 3 files changed, 26 insertions(+), 18 deletions(-) >> >> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h >> index 9926556099ae..823805cc465a 100644 >> --- a/arch/riscv/include/asm/pgtable.h >> +++ b/arch/riscv/include/asm/pgtable.h >> @@ -578,6 +578,14 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf, >> if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVVPTC)) >> return; >> >> + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL)) { >> + local_sfence_w_inval(); >> + while (nr--) >> + local_sinval_vma(address + nr * PAGE_SIZE, asid); 'asid' is not initialized here. The following fixup is needed: diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 3c17ad0786ab..e283649e1dee 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -570,32 +570,32 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf,         /*          * Svvptc guarantees that the new valid pte will be visible within          * a bounded timeframe, so when the uarch does not cache invalid          * entries, we don't have to do anything.          */         if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVVPTC))                 return; +       asid = get_mm_asid(vma->vm_mm);         if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL)) {                 local_sfence_w_inval();                 while (nr--)                         local_sinval_vma(address + nr * PAGE_SIZE, asid);                 local_sfence_inval_ir();                 return;         }         /*          * The kernel assumes that TLBs don't cache invalid entries, but          * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a          * cache flush; it is necessary even after writing invalid entries.          * Relying on flush_tlb_fix_spurious_fault would suffice, but          * the extra traps reduce performance.  So, eagerly SFENCE.VMA.          */ -       asid = get_mm_asid(vma->vm_mm);         while (nr--)                 local_flush_tlb_page_asid(address + nr * PAGE_SIZE, asid);  }  #define update_mmu_cache(vma, addr, ptep) \         update_mmu_cache_range(NULL, vma, addr, ptep, 1)  #define update_mmu_tlb_range(vma, addr, ptep, nr) \ >> + local_sfence_inval_ir(); >> + return; >> + } >> + >> /* >> * The kernel assumes that TLBs don't cache invalid entries, but >> * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a >> diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h >> index 7c2cd5cc92d3..9636d07fe9ee 100644 >> --- a/arch/riscv/include/asm/tlbflush.h >> +++ b/arch/riscv/include/asm/tlbflush.h >> @@ -20,6 +20,24 @@ static inline unsigned long get_mm_asid(struct mm_struct *mm) >> return mm ? cntx2asid(atomic_long_read(&mm->context.id)) : FLUSH_TLB_NO_ASID; >> } >> >> +static inline void local_sfence_inval_ir(void) >> +{ >> + asm volatile(SFENCE_INVAL_IR() ::: "memory"); >> +} >> + >> +static inline void local_sfence_w_inval(void) >> +{ >> + asm volatile(SFENCE_W_INVAL() ::: "memory"); >> +} >> + >> +static inline void local_sinval_vma(unsigned long vma, unsigned long asid) >> +{ >> + if (asid != FLUSH_TLB_NO_ASID) >> + asm volatile(SINVAL_VMA(%0, %1) : : "r" (vma), "r" (asid) : "memory"); >> + else >> + asm volatile(SINVAL_VMA(%0, zero) : : "r" (vma) : "memory"); >> +} >> + >> static inline void local_flush_tlb_all(void) >> { >> __asm__ __volatile__ ("sfence.vma" : : : "memory"); >> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c >> index 73c226f719c7..962db300a166 100644 >> --- a/arch/riscv/mm/tlbflush.c >> +++ b/arch/riscv/mm/tlbflush.c >> @@ -11,24 +11,6 @@ >> >> #define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) >> >> -static inline void local_sfence_inval_ir(void) >> -{ >> - asm volatile(SFENCE_INVAL_IR() ::: "memory"); >> -} >> - >> -static inline void local_sfence_w_inval(void) >> -{ >> - asm volatile(SFENCE_W_INVAL() ::: "memory"); >> -} >> - >> -static inline void local_sinval_vma(unsigned long vma, unsigned long asid) >> -{ >> - if (asid != FLUSH_TLB_NO_ASID) >> - asm volatile(SINVAL_VMA(%0, %1) : : "r" (vma), "r" (asid) : "memory"); >> - else >> - asm volatile(SINVAL_VMA(%0, zero) : : "r" (vma) : "memory"); >> -} >> - >> /* >> * Flush entire TLB if number of entries to be flushed is greater >> * than the threshold below. >> -- >> 2.39.5 >> Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland