From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CF8A19B5B1 for ; Tue, 25 Mar 2025 18:42:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742928128; cv=none; b=dB9TlDlIQLIJosE4dbXysy3H4i5b1KxztLGYcs251Z6pGirYAHNM5zk6fhgBqNhQCclRLM1fJdkFCRWc5La8lFIQ1p15mT9wU4l2P1MjY4hfj3ayFdlSJvuA5aMYLATAUvosWopJEQmjnwmMcUEP+tQq3pewEiKWMKFiLZvFTcU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742928128; c=relaxed/simple; bh=czQfqjHXT8AC/TqCowPb/ICdTvn8xVWPY8Fynodl96M=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=hwAU44cu2oYxHRtGxCdu1wHOhXxCPlLAv5H0XcEuMonaJgB/rmY0S0kI8WL24XbTZrFFvtfojD6xzEPvtxCHra5xtAXDrJ+j5yrqucX/xv+pA01rAS8BuutgonUaA6pic3T+CVXA0VsDkaZ1Dcl9hawP9YbQ2gjuFoqina32R4I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aT9YSFk6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aT9YSFk6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52DDCC4CEE4; Tue, 25 Mar 2025 18:42:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742928128; bh=czQfqjHXT8AC/TqCowPb/ICdTvn8xVWPY8Fynodl96M=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=aT9YSFk6b9jkufAk8kVmC33X31kyb1aWzVts36xbMEwix/lf/heysclGqCnFWMPaQ M5fMzZCi7tLYMYeqIBepcMRgQ2BNS5aprNXd7kk/JaSgkzmF8w0s++eF3RHz85xPW3 Za3LXHmNDwDoGTBQPSuJAAZZXRCZ+SUeN5BTpLJO/ru3v6BdDprTljPvvWL1L41c1U khocGo3TsCC4vXVEbKHQ3NMznx6LrPG4Y2tJV7hCM7M+ACTtq7pQq+e8qaf+GoWNEC Z+oTMtpEwl/akWMEoj3TovduRdJQ5FgkGzQZT7YhR9xOd8IlUMyn3TxNeleTcsQLO9 aUidFygrY1VaA== Message-ID: Date: Tue, 25 Mar 2025 19:42:03 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] clocksource/drivers/nxp-timer: Add the System Timer Module for the s32g platform To: Daniel Lezcano , tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Thomas Fossati , Larisa Grigore , Ghennadi Procopciuc , Maxime Coquelin , Alexandre Torgue , "moderated list:ARM/STM32 ARCHITECTURE" , "moderated list:ARM/STM32 ARCHITECTURE" , dl-S32 References: <20250324100008.346009-1-daniel.lezcano@linaro.org> <20250324100008.346009-2-daniel.lezcano@linaro.org> <1bf2d9ad-325e-4b1d-8440-ddbc90eabc67@linaro.org> <9ca80442-15c8-4f2d-ac11-8096b2cd83ad@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 25/03/2025 19:38, Daniel Lezcano wrote: > On 25/03/2025 13:30, Krzysztof Kozlowski wrote: >> On 25/03/2025 13:23, Daniel Lezcano wrote: > > [ ... ] > >>>>> + if (!stm_instances->clocksource && (stm_instances->features & STM_CLKSRC)) { >>>>> + >>>>> + /* >>>>> + * First probed STM will be a clocksource >>>>> + */ >>>>> + ret = nxp_stm_clocksource_init(dev, name, base, clk); >>>>> + if (ret) >>>>> + return ret; >>>>> + stm_instances->clocksource++; >>>> >>>> That's racy. Devices can be brought async, ideally. This should be >>>> rather idr or probably entire structure protected with a mutex. >>> >>> Mmh, interesting. I never had to think about this problem before >>> >>> Do you know at what moment the probing is parallelized ? >> >> You don't have PROBE_PREFER_ASYNCHRONOUS, so currently this will be >> still sync, but I don't think we want it to be that way forever. I think >> new drivers should not rely on implicit sync, because converting it >> later to async will be difficult. It's easier to design it now or even >> choose async explicitly (after testing). > > I gave a try and sometimes I reach the warnings below. I suspect the > underlying code in the time framework is not yet ready for that. > > Even if it could be a good candidate for parallelizing the boot, this > driver should stay sync ATM. Except if someone has the willing to dig > into the core framework to find out the race when switching the > clockevent. I think a thread is setting a timer while we are switching > the driver. > > IMO, this core framework is too sensitive for this kind of change now. > > Alternatively, I can put anyway the lock which is harmless for the sync > code but making the driver race free. The async flag can be put later. Yes, that's what I meant, although indeed good point that clocksource is way too early to be async. In that case this part is up to you, maybe my suggestion was not correct. Best regards, Krzysztof