From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754045AbdAZVjs (ORCPT ); Thu, 26 Jan 2017 16:39:48 -0500 Received: from mail-wm0-f42.google.com ([74.125.82.42]:37219 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753842AbdAZVjp (ORCPT ); Thu, 26 Jan 2017 16:39:45 -0500 Subject: Re: [PATCH v2] clk: qcom: gdsc: Fix handling of hw control enable/disable To: Rajendra Nayak , sboyd@codeaurora.org, mturquette@baylibre.com References: <1485145581-517-1-git-send-email-rnayak@codeaurora.org> Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, sricharan@codeaurora.org From: Stanimir Varbanov Message-ID: Date: Thu, 26 Jan 2017 23:31:03 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <1485145581-517-1-git-send-email-rnayak@codeaurora.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Thanks for the patch! On 23.01.2017 06:26, Rajendra Nayak wrote: > Once a gdsc is brought in and out of HW control, there is a > power down and up cycle which can take upto 1us. Polling on > the gdsc status immediately after the hw control enable/disable > can mislead software/firmware to belive the gdsc is already either on > or off, while its yet to complete the power cycle. > To avoid this add a 1us delay post a enable/disable of HW control > mode. > > Also after the HW control mode is disabled, poll on the status to > check gdsc status reflects its 'on' before force disabling it > in software. > > Reported-by: Stanimir Varbanov > Signed-off-by: Rajendra Nayak > --- > drivers/clk/qcom/gdsc.c | 58 ++++++++++++++++++++++++++++++++++++++----------- > 1 file changed, 45 insertions(+), 13 deletions(-) Reviewed and Tested-by: Stanimir Varbanov regards, Stan