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Tue, 20 Oct 2026 21:56:48 -0400 From: Jonathan Santos To: , , , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH v4 1/9] spi: dt-bindings: Add spi-cs-composite property Date: Tue, 20 Oct 2026 22:56:41 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAwNyBTYWx0ZWRfX1DBYkdYc+qCy AWsKvOJu6jYJoSuJ2xTpxXL6GXXJ1efX522HQmLJ4I4uaj+eKcfOZdKDc2KrXr+8kMy9qvaBeA9 hFOToS4ZRc1GHMkd6muYFoR8pS8IuqhQN/apbFJByw7IWuy1mmDPVD0jSHNz4sajh5BVbOitSyo zvE0HUvxubnEmuIDD95D8oDwz62IP3V6cB5/O7Z1Uc7V0+UssvTmcqxBdvMVfAe3W0yfF+Apewi Dx3r/YaZLpl+UL0ob4onuGYfI0xpng34RDQfgbWZYJwIRxq+Kw06JJAbR3Xl7u0g+LPJPo4qi8I iacFWQuOvI8a3AyJtYIAulzH/RFHwdxtQ7l4lTtbjRte5uUH/XeNysL7v38+xyqICwqrt2mXjbZ +BqP5gx6uAvzwGmMNGdsqnCT2N6RBih9OZK/Wx5MDrGIWY9w7pua+bFfp2uau2qlanPF61nFEJi bkxxYK1EG1CfZTZeVxg== X-Proofpoint-GUID: Aj5ZPDt2mb-2oCfk-ceEr7PMwQWA_raQ X-Authority-Analysis: v=2.4 cv=KIHPn1Fo c=1 sm=1 tr=0 ts=6ad81bec cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=660iZSQnnn4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=uXIjobp8t2wMuQ0fPvqm:22 a=gAnH3GRIAAAA:8 a=Nsxvo0O3_Z_9E4ZUgYQA:9 X-Proofpoint-ORIG-GUID: Aj5ZPDt2mb-2oCfk-ceEr7PMwQWA_raQ X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAwNyBTYWx0ZWRfX+26lqo1BQH0n Gf+6gd0w11WPiyG8ssKDxfa+/T2PsSpP2FdpPMFHDaMLxwMurfMwXwbusmpv59wr1hZMxdYsBwt 7phhDuPEgRebAiodgfoS0voqE47Pa+a/xKIV47nO+QyWiq6mjdVx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-20_04,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 suspectscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210007 Some setups combine several SPI devices into one logical device, with each chip on its own CS line. All of those CS lines must be asserted at the same time, so that one transfer reaches every chip. Add the 'spi-cs-composite' boolean property. When it is set, every chip select listed in 'reg' is asserted together on each transfer. Signed-off-by: Jonathan Santos --- Changes in v4: * New patch. This has been included because without an explicit property, every device with more than one 'reg' entry would have all its chip selects asserted together. That breaks devices that use ancillary devices for the extra CS lines, so the composite behavior is now opt-in. --- .../devicetree/bindings/spi/spi-peripheral-props.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 4894196c8f9c..456cb9095632 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -60,6 +60,14 @@ properties: Delay in nanoseconds to be introduced by the controller after CS is de-asserted. + spi-cs-composite: + description: Some SPI devices can be aggregated into a single logical + device by asserting all their chip selects simultaneously. When this + property is present, all chip selects listed in the 'reg' property are + asserted together on every transfer, treating the group as one composite + device. + type: boolean + spi-rx-bus-width: description: Bus width to the SPI bus used for read transfers. -- 2.34.1