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([2600:1700:e321:62f0:da43:aeff:fecc:bfd5]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1270433abdfsm11577096c88.12.2026.02.10.08.02.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Feb 2026 08:02:36 -0800 (PST) Sender: Guenter Roeck Message-ID: Date: Tue, 10 Feb 2026 08:02:34 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/2] watchdog: npcm: Add reset status support To: Tomer Maimon , andrew@codeconstruct.com.au, avifishman70@gmail.com, tali.perry1@gmail.com, wim@linux-watchdog.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: venture@google.com, yuenn@google.com, benjaminfair@google.com, joel@jms.id.au, openbmc@lists.ozlabs.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260210133843.1078463-1-tmaimon77@gmail.com> <20260210133843.1078463-3-tmaimon77@gmail.com> Content-Language: en-US From: Guenter Roeck Autocrypt: addr=linux@roeck-us.net; keydata= xsFNBE6H1WcBEACu6jIcw5kZ5dGeJ7E7B2uweQR/4FGxH10/H1O1+ApmcQ9i87XdZQiB9cpN RYHA7RCEK2dh6dDccykQk3bC90xXMPg+O3R+C/SkwcnUak1UZaeK/SwQbq/t0tkMzYDRxfJ7 nyFiKxUehbNF3r9qlJgPqONwX5vJy4/GvDHdddSCxV41P/ejsZ8PykxyJs98UWhF54tGRWFl 7i1xvaDB9lN5WTLRKSO7wICuLiSz5WZHXMkyF4d+/O5ll7yz/o/JxK5vO/sduYDIlFTvBZDh gzaEtNf5tQjsjG4io8E0Yq0ViobLkS2RTNZT8ICq/Jmvl0SpbHRvYwa2DhNsK0YjHFQBB0FX IdhdUEzNefcNcYvqigJpdICoP2e4yJSyflHFO4dr0OrdnGLe1Zi/8Xo/2+M1dSSEt196rXaC kwu2KgIgmkRBb3cp2vIBBIIowU8W3qC1+w+RdMUrZxKGWJ3juwcgveJlzMpMZNyM1jobSXZ0 VHGMNJ3MwXlrEFPXaYJgibcg6brM6wGfX/LBvc/haWw4yO24lT5eitm4UBdIy9pKkKmHHh7s jfZJkB5fWKVdoCv/omy6UyH6ykLOPFugl+hVL2Prf8xrXuZe1CMS7ID9Lc8FaL1ROIN/W8Vk BIsJMaWOhks//7d92Uf3EArDlDShwR2+D+AMon8NULuLBHiEUQARAQABzTJHdWVudGVyIFJv ZWNrIChMaW51eCBhY2NvdW50KSA8bGludXhAcm9lY2stdXMubmV0PsLBgQQTAQIAKwIbAwYL CQgHAwIGFQgCCQoLBBYCAwECHgECF4ACGQEFAmgrMyQFCSbODQkACgkQyx8mb86fmYGcWRAA oRwrk7V8fULqnGGpBIjp7pvR187Yzx+lhMGUHuM5H56TFEqeVwCMLWB2x1YRolYbY4MEFlQg VUFcfeW0OknSr1s6wtrtQm0gdkolM8OcCL9ptTHOg1mmXa4YpW8QJiL0AVtbpE9BroeWGl9v 2TGILPm9mVp+GmMQgkNeCS7Jonq5f5pDUGumAMguWzMFEg+Imt9wr2YA7aGen7KPSqJeQPpj onPKhu7O/KJKkuC50ylxizHzmGx+IUSmOZxN950pZUFvVZH9CwhAAl+NYUtcF5ry/uSYG2U7 DCvpzqOryJRemKN63qt1bjF6cltsXwxjKOw6CvdjJYA3n6xCWLuJ6yk6CAy1Ukh545NhgBAs rGGVkl6TUBi0ixL3EF3RWLa9IMDcHN32r7OBhw6vbul8HqyTFZWY2ksTvlTl+qG3zV6AJuzT WdXmbcKN+TdhO5XlxVlbZoCm7ViBj1+PvIFQZCnLAhqSd/DJlhaq8fFXx1dCUPgQDcD+wo65 qulV/NijfU8bzFfEPgYP/3LP+BSAyFs33y/mdP8kbMxSCjnLEhimQMrSSo/To1Gxp5C97fw5 3m1CaMILGKCmfI1B8iA8zd8ib7t1Rg0qCwcAnvsM36SkrID32GfFbv873bNskJCHAISK3Xkz qo7IYZmjk/IJGbsiGzxUhvicwkgKE9r7a1rOwU0ETofVZwEQALlLbQeBDTDbwQYrj0gbx3bq 7kpKABxN2MqeuqGr02DpS9883d/t7ontxasXoEz2GTioevvRmllJlPQERVxM8gQoNg22twF7 pB/zsrIjxkE9heE4wYfN1AyzT+AxgYN6f8hVQ7Nrc9XgZZe+8IkuW/Nf64KzNJXnSH4u6nJM J2+Dt274YoFcXR1nG76Q259mKwzbCukKbd6piL+VsT/qBrLhZe9Ivbjq5WMdkQKnP7gYKCAi pNVJC4enWfivZsYupMd9qn7Uv/oCZDYoBTdMSBUblaLMwlcjnPpOYK5rfHvC4opxl+P/Vzyz 6WC2TLkPtKvYvXmdsI6rnEI4Uucg0Au/Ulg7aqqKhzGPIbVaL+U0Wk82nz6hz+WP2ggTrY1w ZlPlRt8WM9w6WfLf2j+PuGklj37m+KvaOEfLsF1v464dSpy1tQVHhhp8LFTxh/6RWkRIR2uF I4v3Xu/k5D0LhaZHpQ4C+xKsQxpTGuYh2tnRaRL14YMW1dlI3HfeB2gj7Yc8XdHh9vkpPyuT nY/ZsFbnvBtiw7GchKKri2gDhRb2QNNDyBnQn5mRFw7CyuFclAksOdV/sdpQnYlYcRQWOUGY HhQ5eqTRZjm9z+qQe/T0HQpmiPTqQcIaG/edgKVTUjITfA7AJMKLQHgp04Vylb+G6jocnQQX JqvvP09whbqrABEBAAHCwWUEGAECAA8CGwwFAmgrMyQFCSbODQkACgkQyx8mb86fmYHlgg/9 H5JeDmB4jsreE9Bn621wZk7NMzxy9STxiVKSh8Mq4pb+IDu1RU2iLyetCY1TiJlcxnE362kj njrfAdqyPteHM+LU59NtEbGwrfcXdQoh4XdMuPA5ADetPLma3YiRa3VsVkLwpnR7ilgwQw6u dycEaOxQ7LUXCs0JaGVVP25Z2hMkHBwx6BlW6EZLNgzGI2rswSZ7SKcsBd1IRHVf0miwIFYy j/UEfAFNW+tbtKPNn3xZTLs3quQN7GdYLh+J0XxITpBZaFOpwEKV+VS36pSLnNl0T5wm0E/y scPJ0OVY7ly5Vm1nnoH4licaU5Y1nSkFR/j2douI5P7Cj687WuNMC6CcFd6j72kRfxklOqXw zvy+2NEcXyziiLXp84130yxAKXfluax9sZhhrhKT6VrD45S6N3HxJpXQ/RY/EX35neH2/F7B RgSloce2+zWfpELyS1qRkCUTt1tlGV2p+y2BPfXzrHn2vxvbhEn1QpQ6t+85FKN8YEhJEygJ F0WaMvQMNrk9UAUziVcUkLU52NS9SXqpVg8vgrO0JKx97IXFPcNh0DWsSj/0Y8HO/RDkGXYn FDMj7fZSPKyPQPmEHg+W/KzxSSfdgWIHF2QaQ0b2q1wOSec4Rti52ohmNSY+KNIW/zODhugJ np3900V20aS7eD9K8GTU0TGC1pyz6IVJwIE= In-Reply-To: <20260210133843.1078463-3-tmaimon77@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2/10/26 05:38, Tomer Maimon wrote: > Add reset status detection for NPCM watchdog driver on both NPCM7XX and > NPCM8XX platforms. Implement GCR register integration via syscon for > reset status detection and configurable reset type mapping via device > tree properties. > > Signed-off-by: Tomer Maimon > --- > drivers/watchdog/npcm_wdt.c | 110 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 110 insertions(+) > > diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c > index e62ea054bc61..ebece5d6240a 100644 > --- a/drivers/watchdog/npcm_wdt.c > +++ b/drivers/watchdog/npcm_wdt.c > @@ -12,9 +12,25 @@ > #include > #include > #include > +#include > +#include > + > +#define NPCM7XX_RESSR_OFFSET 0x6C > +#define NPCM7XX_INTCR2_OFFSET 0x60 > > #define NPCM_WTCR 0x1C > > +#define NPCM7XX_PORST BIT(31) > +#define NPCM7XX_CORST BIT(30) > +#define NPCM7XX_WD0RST BIT(29) > +#define NPCM7XX_WD1RST BIT(24) > +#define NPCM7XX_WD2RST BIT(23) > +#define NPCM7XX_SWR1RST BIT(28) > +#define NPCM7XX_SWR2RST BIT(27) > +#define NPCM7XX_SWR3RST BIT(26) > +#define NPCM7XX_SWR4RST BIT(25) > +#define NPCM8XX_RST (GENMASK(31, 23) | GENMASK(15, 12)) > + > #define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */ > #define NPCM_WTE BIT(7) /* Enable */ > #define NPCM_WTIE BIT(6) /* Enable irq */ > @@ -45,6 +61,9 @@ struct npcm_wdt { > struct watchdog_device wdd; > void __iomem *reg; > struct clk *clk; > + u32 card_reset; > + u32 ext1_reset; > + u32 ext2_reset; > }; > > static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd) > @@ -185,6 +204,95 @@ static const struct watchdog_ops npcm_wdt_ops = { > .restart = npcm_wdt_restart, > }; > > +static u32 npcm_wdt_reset_type(const char *reset_type) > +{ > + if (!strcmp(reset_type, "porst")) > + return NPCM7XX_PORST; > + else if (!strcmp(reset_type, "corst")) > + return NPCM7XX_CORST; > + else if (!strcmp(reset_type, "wd0")) > + return NPCM7XX_WD0RST; > + else if (!strcmp(reset_type, "wd1")) > + return NPCM7XX_WD1RST; > + else if (!strcmp(reset_type, "wd2")) > + return NPCM7XX_WD2RST; > + else if (!strcmp(reset_type, "sw1")) > + return NPCM7XX_SWR1RST; > + else if (!strcmp(reset_type, "sw2")) > + return NPCM7XX_SWR2RST; > + else if (!strcmp(reset_type, "sw3")) > + return NPCM7XX_SWR3RST; > + else if (!strcmp(reset_type, "sw4")) > + return NPCM7XX_SWR4RST; > + > + return 0; > +} > + > +static void npcm_get_reset_status(struct npcm_wdt *wdt, struct device *dev) > +{ > + const char *card_reset_type; > + const char *ext1_reset_type; > + const char *ext2_reset_type; > + struct regmap *gcr_regmap; > + u32 rstval, ressrval; > + int ret; > + > + gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon"); > + if (IS_ERR(gcr_regmap)) { > + dev_warn(dev, "Failed to find gcr syscon, WD reset status not supported\n"); A warning is quite strong here, given that this is new code and the syscon reference may not exist in existing devicetree files. notice should be good enough. > + return; > + } > + > + ret = of_property_read_string(dev->of_node, > + "nuvoton,card-reset-type", > + &card_reset_type); > + if (ret) > + wdt->card_reset = NPCM7XX_PORST; > + else > + wdt->card_reset = npcm_wdt_reset_type(card_reset_type); > + > + ret = of_property_read_string(dev->of_node, > + "nuvoton,ext1-reset-type", > + &ext1_reset_type); > + if (ret) > + wdt->ext1_reset = 0; wdt is zero-allocated, so setting those variables to 0 is not necessary. > + else > + wdt->ext1_reset = npcm_wdt_reset_type(ext1_reset_type); > + > + ret = of_property_read_string(dev->of_node, > + "nuvoton,ext2-reset-type", > + &ext2_reset_type); > + if (ret) > + wdt->ext2_reset = 0; > + else > + wdt->ext2_reset = npcm_wdt_reset_type(ext2_reset_type); > + > + regmap_read(gcr_regmap, NPCM7XX_INTCR2_OFFSET, &rstval); This warrants an explanation/comment: Why is it not necessary to check the return value of the regmap operations ? > + /* prefer the most specific SoC first */ > + if (of_device_is_compatible(dev->of_node, "nuvoton,npcm845-wdt")) { > + regmap_write(gcr_regmap, NPCM7XX_INTCR2_OFFSET, > + rstval & ~NPCM8XX_RST); > + } else if (of_device_is_compatible(dev->of_node, "nuvoton,npcm750-wdt")) { > + if ((rstval & NPCM7XX_PORST) == 0) { > + rstval = NPCM7XX_PORST; > + regmap_write(gcr_regmap, NPCM7XX_INTCR2_OFFSET, > + rstval | NPCM7XX_PORST); That "| NPCM7XX_PORST" is pretty pointless here since rstval was just set to that value. > + } else { > + rstval = 0; > + } Another comment needed: This negates NPCM7XX_PORST and otherwise clear rstval. The reason is not immediately (or, rather, at all) obvious. > + regmap_read(gcr_regmap, NPCM7XX_RESSR_OFFSET, &ressrval); > + rstval |= ressrval; > + regmap_write(gcr_regmap, NPCM7XX_RESSR_OFFSET, ressrval); > + } If the device is not compatible to either chip, retval is just passed on and nothing is written to the chip. That warrants another comment. [ Yes, I see that the driver does not currently support another chip. > + > + if (rstval & wdt->card_reset) > + wdt->wdd.bootstatus |= WDIOF_CARDRESET; > + if (rstval & wdt->ext1_reset) > + wdt->wdd.bootstatus |= WDIOF_EXTERN1; > + if (rstval & wdt->ext2_reset) > + wdt->wdd.bootstatus |= WDIOF_EXTERN2; > +} > + > static int npcm_wdt_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > @@ -208,6 +316,8 @@ static int npcm_wdt_probe(struct platform_device *pdev) > if (irq < 0) > return irq; > > + npcm_get_reset_status(wdt, dev); > + > wdt->wdd.info = &npcm_wdt_info; > wdt->wdd.ops = &npcm_wdt_ops; > wdt->wdd.min_timeout = 1;