From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m1973189.qiye.163.com (mail-m1973189.qiye.163.com [220.197.31.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93A361A6812; Wed, 11 Mar 2026 05:41:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.89 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773207721; cv=none; b=JD0QdCQd9erUPW0KE0C7qbXMK0qzA3cK2ix6RKtP7zUzg5GURlTGaTr0zqmwi7weBYuyX+/eSXONa3eAHbb+3pBhAedO7FS2XYOe7uhwJ45q7dhmmFeiCmfRwdn5LmB3fx+/xkBn6L54B+BqbPjCuKiuiXun3d8L8GpJLX6ULQo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773207721; c=relaxed/simple; bh=eZq62JBHkK1Ju69MukNzvda0TQ1C2GpK9Gtc7lrsaiI=; h=Cc:Subject:To:References:From:Message-ID:Date:MIME-Version: In-Reply-To:Content-Type; b=hdlqHsayzVB6HahnWQ/Hfg3LigYtULzpPLSoZbk1cPb75XuTs/9hK/QlP40xDwSYN8p+ec2cCQgOHz8ThBS6foiV7zflyjWrRVWeCgs1cbU2J5vyuQ4XEfaHYTkufrrzTFJqGmo6Jamnk92p1yH8tEab7LzXrd73+Toh9apt9L0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=K7wZRUJk; arc=none smtp.client-ip=220.197.31.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="K7wZRUJk" Received: from [172.16.12.17] (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 36820e818; Wed, 11 Mar 2026 13:26:29 +0800 (GMT+08:00) Cc: shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Niklas Cassel , Wilfred Mallawa , Krishna Chaitanya Chundru , Lukas Wunner , Richard Zhu , Brian Norris , Wilson Ding , Frank Li Subject: Re: [PATCH v7 1/4] PCI/ERR: Add support for resetting the Root Ports in a platform specific way To: manivannan.sadhasivam@oss.qualcomm.com, Bjorn Helgaas , Mahesh J Salgaonkar , Oliver O'Halloran , Will Deacon , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Manivannan Sadhasivam , Rob Herring , Heiko Stuebner , Philipp Zabel References: <20260310-pci-port-reset-v7-0-9dd00ccc25ab@oss.qualcomm.com> <20260310-pci-port-reset-v7-1-9dd00ccc25ab@oss.qualcomm.com> From: Shawn Lin Message-ID: Date: Wed, 11 Mar 2026 13:26:28 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: <20260310-pci-port-reset-v7-1-9dd00ccc25ab@oss.qualcomm.com> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit X-HM-Tid: 0a9cdb5c5d4d09cckunma929f57d18cd2d X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQhlDTlZPHxlISE4ZSx8aHUJWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=K7wZRUJk1emUgxCcHil5+9JB/ANF+IxeKRXJYfvQNEB51UFMvURGvaB1+hEuaGfLw6gNqqGdYK7+AzOAJqC3QeulrOvdMdg98utMWmVdILteJwz08dWusEIiUceoqY1rrzpiBbUcuejudxcc0a8Y5GCv3zU3YmURNiNhYMC2e6Q=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=9yG8NQ0gHRExp7u3DqeTqLY+f4Q07ToFiRLsE78NeCU=; h=date:mime-version:subject:message-id:from; ÔÚ 2026/03/10 ÐÇÆÚ¶þ 22:01, Manivannan Sadhasivam via B4 Relay дµÀ: > From: Manivannan Sadhasivam > > Some host bridge devices require resetting the Root Ports in a platform > specific way to recover them from error conditions such as Fatal AER > errors, Link Down etc... So introduce pci_host_bridge::reset_root_port() > callback and call it from pcibios_reset_secondary_bus() if available. Also, > save the Root Port config space before reset and restore it afterwards. > > The 'reset_root_port' callback is responsible for resetting the given Root > Port referenced by the 'pci_dev' pointer in a platform specific way and > bring it back to the working state if possible. If any error occurs during > the reset operation, relevant errno should be returned. > > Signed-off-by: Manivannan Sadhasivam > Signed-off-by: Manivannan Sadhasivam > Tested-by: Brian Norris > Tested-by: Krishna Chaitanya Chundru > Tested-by: Richard Zhu > Reviewed-by: Frank Li > --- > drivers/pci/pci.c | 20 ++++++++++++++++++++ > drivers/pci/pcie/err.c | 5 ----- > include/linux/pci.h | 1 + > 3 files changed, 21 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 8479c2e1f74f..6f09057d83e0 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -4812,6 +4812,26 @@ void pci_reset_secondary_bus(struct pci_dev *dev) > > void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) > { > + struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); > + int ret; > + > + if (pci_is_root_bus(dev->bus) && host->reset_root_port) { > + /* > + * Save the config space of the Root Port before doing the > + * reset, since the state could be lost. The Endpoint state > + * should've been saved by the caller. > + */ > + pci_save_state(dev); > + ret = host->reset_root_port(host, dev); > + if (ret) > + pci_err(dev, "Failed to reset Root Port: %d\n", ret); > + else > + /* Now restore it on success */ > + pci_restore_state(dev); > + > + return; > + } > + > pci_reset_secondary_bus(dev); > } > LGTM, Reviewed-by: Shawn Lin > diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c > index bebe4bc111d7..13b9d9eb714f 100644 > --- a/drivers/pci/pcie/err.c > +++ b/drivers/pci/pcie/err.c > @@ -256,11 +256,6 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, > } > > if (status == PCI_ERS_RESULT_NEED_RESET) { > - /* > - * TODO: Should call platform-specific > - * functions to reset slot before calling > - * drivers' slot_reset callbacks? > - */ > status = PCI_ERS_RESULT_RECOVERED; > pci_dbg(bridge, "broadcast slot_reset message\n"); > pci_walk_bridge(bridge, report_slot_reset, &status); > diff --git a/include/linux/pci.h b/include/linux/pci.h > index 1c270f1d5123..34c434b79abb 100644 > --- a/include/linux/pci.h > +++ b/include/linux/pci.h > @@ -644,6 +644,7 @@ struct pci_host_bridge { > void (*release_fn)(struct pci_host_bridge *); > int (*enable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); > void (*disable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); > + int (*reset_root_port)(struct pci_host_bridge *bridge, struct pci_dev *dev); > void *release_data; > unsigned int ignore_reset_delay:1; /* For entire hierarchy */ > unsigned int no_ext_tags:1; /* No Extended Tags */ >