From: Shrikanth Hegde <sshegde@linux.vnet.ibm.com>
To: Ingo Molnar <mingo@kernel.org>
Cc: mingo@redhat.com, peterz@infradead.org,
vincent.guittot@linaro.org, dietmar.eggemann@arm.com,
vschneid@redhat.com, linux-kernel@vger.kernel.org,
srikar@linux.vnet.ibm.com, mgorman@techsingularity.net,
yu.c.chen@intel.com, ricardo.neri-calderon@linux.intel.com,
iamjoonsoo.kim@lge.com, tim.c.chen@linux.intel.com,
juri.lelli@redhat.com, rocking@linux.alibaba.com,
joshdon@google.com
Subject: Re: [PATCH] sched/fair: optimize should_we_balance for higher SMT systems
Date: Wed, 6 Sep 2023 07:18:09 +0530 [thread overview]
Message-ID: <e96c04b2-0c63-74f7-b7ca-357177ef3eb7@linux.vnet.ibm.com> (raw)
In-Reply-To: <ZPMVcTFmtvshJRYH@gmail.com>
On 9/2/23 4:28 PM, Ingo Molnar wrote:
>
> * Shrikanth Hegde <sshegde@linux.vnet.ibm.com> wrote:
>
>> should_we_balance is called in load_balance to find out if the CPU that
>> is trying to do the load balance is the right one or not.
>> With commit b1bfeab9b002("sched/fair: Consider the idle state of the whole
>> core for load balance"), tries to find an idle core to do the load balancing
>> and fallsback on an idle sibling CPU if there is no idle core.
>>
>> However, on larger SMT systems, it could be needlessly iterating to find a
>> idle by scanning all the CPUs in an non-idle core. If the core is not idle,
>> and first SMT sibling which is idle has been found, then its not needed to
>> check other SMT siblings for idleness
>>
>> Lets say in SMT4, Core0 has 0,2,4,6 and CPU0 is BUSY and rest are IDLE.
>> balancing domain is MC/DIE. CPU2 will be set as the first idle_smt and
>> same process would be repeated for CPU4 and CPU6 but this is unnecessary.
>> Since calling is_core_idle loops through all CPU's in the SMT mask, effect
>> is multiplied by weight of smt_mask. For example,when say 1 CPU is busy,
>> we would skip loop for 2 CPU's and skip iterating over 8CPU's. That
>> effect would be more in DIE/NUMA domain where there are more cores.
>>
>> Testing and performance evaluation
>> The test has been done on this system which has 12 cores, i.e 24 small
>> cores with SMT=4
>> lscpu
>> Architecture: ppc64le
>> Byte Order: Little Endian
>> CPU(s): 96
>> On-line CPU(s) list: 0-95
>> Model name: POWER10 (architected), altivec supported
>> Thread(s) per core: 8
>
> Ok, so the performance figures are pretty convincing, and the approach
> is fairly simple - so I've applied your patch to tip:sched/urgent,
> to address the performance regression caused by b1bfeab9b002.
>
> Thanks,
>
> Ingo
Thank you Ingo.
next prev parent reply other threads:[~2023-09-06 1:48 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-02 8:12 Shrikanth Hegde
2023-09-02 10:58 ` Ingo Molnar
2023-09-06 1:48 ` Shrikanth Hegde [this message]
2023-09-02 16:17 ` [tip: sched/urgent] sched/fair: Optimize should_we_balance() for large " tip-bot2 for Shrikanth Hegde
2023-09-05 19:30 ` [PATCH] sched/fair: optimize should_we_balance for higher " Tim Chen
2023-09-06 2:06 ` Shrikanth Hegde
2023-09-06 15:56 ` Tim Chen
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