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Fri, 25 Apr 2025 05:19:31 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53P5JUcp025931 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Apr 2025 05:19:30 GMT Received: from [10.47.235.76] (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Apr 2025 22:19:29 -0700 Message-ID: Date: Thu, 24 Apr 2025 22:19:29 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] dt-bindings: arm: qcom: add SA8255p Ride board To: Krzysztof Kozlowski , , , , , CC: , , , , , References: <20250423003845.3980330-1-quic_djaggi@quicinc.com> <1d75a955-409a-409e-8708-754e89d6f046@linaro.org> <21a13826-0ee3-486a-956c-153f42477160@quicinc.com> <121d4e01-00cd-4be5-acbb-b140188048c3@linaro.org> Content-Language: en-US From: Deepti Jaggi In-Reply-To: <121d4e01-00cd-4be5-acbb-b140188048c3@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI1MDAzNiBTYWx0ZWRfXzHgpZCNqB322 /b5/Q6mgse5rXqhveOx78VhN7s7D7ab2VH1DiXw8m0Z7h2i/ReumY226hYnxs3oS6387vFytp3u mgk9StcH21SrsTn9fKKaoyW43W+mrdH+CD2RQN7VSHfjx2qWD7izc3v3EHeWK5dqCcQEXjdiPJw 841PXUa1fYOVlMoqA1Rt45hivb/PN5/b2w0BP/6e0GfBMRp19mTNp1AMO8TRFYci3COPFrWK7zE p+j+ZbUW++EunIIRmaVygQQ0f8mLJ3F+NteYRj6QYgz64MizYFBqBLhgQQRXMqtd2UmYYCZ1xSv xzKKFcEdpxv7yrcdvbOhdB5FPIgSzHSN5tRrlqHDCYL08YY9y3tY8yEk5SjBXXdoJoKY+SUe1Co H+Ck0yHdv0hTtvMDFmXUy/PfDoBZHHd6r6VQub8Ln0tUWLeC5gGY2ICK8auItuArMSZ4VJsZ X-Authority-Analysis: v=2.4 cv=bs1MBFai c=1 sm=1 tr=0 ts=680b1b63 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=3H110R4YSZwA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=8Nqr4VOqxz35mBUtWYIA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: HZtQSeEjlGAqBmrSp0nPRT-55wjWOnER X-Proofpoint-GUID: HZtQSeEjlGAqBmrSp0nPRT-55wjWOnER X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-25_01,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 mlxscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504250036 On 4/23/25 23:17, Krzysztof Kozlowski wrote: > On 24/04/2025 01:54, Deepti Jaggi wrote: >> >> On 4/23/25 05:00, Krzysztof Kozlowski wrote: >>> On 23/04/2025 02:38, Deepti Jaggi wrote: >>>> From: Nikunj Kela >>>> >>>> Document the SA8255p SoC and its reference board: sa8255p-ride. >>>> >>>> Reviewed-by: Krzysztof Kozlowski >>>> Signed-off-by: Nikunj Kela >>>> Signed-off-by: Deepti Jaggi >>>> --- >>>> Changes in v3: >>>> Removed the patches from original series[1] >>> >>> Why? This makes no sense on its own. Binding goes with the user. No >>> user? No binding. >> >> Thanks for taking the time to review the patch. >> All the bindings that were initially included in the original series [1] >> were removed and posted as individual patches. >> devicetree has been posted as a separate patch : >> Link: https://lore.kernel.org/all/20250422231249.871995-1-quic_djaggi@quicinc.com >> If necessary, I can consolidate the bindings and dt into a single series >> for the next version. > I asked why and that's not the answer to why. That's description of what > you did, but we see it here. Anyway, I explained you the process. By examining other patches that were split from the series by the author, it appears that it was advised to split the patches based on subsystem. However, I do not have any further details. I followed the approach used for other bindings [1] [2] [3], which were part of the original series and were sent as separate patches and accepted. I misjudged that the SoC binding could also be sent as a separate patch. I will combine the remaining bindings along with the device tree (DT) into a single series in the next revision. [1]: https://lore.kernel.org/all/20240910165926.2408630-1-quic_nkela@quicinc.com/ [2]: https://lore.kernel.org/all/20240910171534.2412263-1-quic_nkela@quicinc.com/ [3]: https://lore.kernel.org/all/20240905194741.3803345-1-quic_nkela@quicinc.com/ > > Best regards, > Krzysztof