From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D062431D730 for ; Fri, 3 Jul 2026 05:07:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783055277; cv=none; b=add9LYnQLnpoc5+jJ46yNndHDIIWbGl6vuzynU30bY/kvPOWHoSCB2qR6fObNLKIZ9DwZQ+xROndfMeA3/ZsEiZn4MJ3gR4QrDxZH3dPSMEP+jamN4zrkfT/tuWPIntk8z6jrs9FQyFWcYpEsB9Rlkz373o9aB+AV3VgEKgMvcA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783055277; c=relaxed/simple; bh=k9XiWI3TNK/R0dGu8CwvcUGF91gLpaB5UfgbTRX11A8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=kJe11AWf6gUfxbzbvOE1NqVCdiS5VNbU3hUOl3SxqEZNV46/HSG6QZuF2jkFahkJsrWNwyynurGeprrlUwb6mpqJyCZfWvlxLclcoL8oUqv0d8b24wIOeS0/2/sl7VV0iUF2kuiVsOoHfHcIJ0XUJJNLHo2HIF7xoFXcOlfuxAo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=NU67JIiO; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="NU67JIiO" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D317822D7; Thu, 2 Jul 2026 22:07:39 -0700 (PDT) Received: from [10.163.170.216] (unknown [10.163.170.216]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A3B3E3F673; Thu, 2 Jul 2026 22:07:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783055264; bh=k9XiWI3TNK/R0dGu8CwvcUGF91gLpaB5UfgbTRX11A8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=NU67JIiOkURmkAc5eZhwVSMA+S/yr+//BgY44DII8lQWoIgLo+6wP/ShBlyl/6b2y 5h1ZDjGjA/2XkZy5i2Uh6e/jXLCSr4dd0uG7OtHQQjb52qPH/8m0p4nWhHsLaF+Nvx QlWooe+RVHL5vXfwVzMq1aWef+RIbZNFefWIhAC4= Message-ID: Date: Fri, 3 Jul 2026 10:37:38 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] arm64: cputype: Add Cortex-A520AE definitions To: Linu Cherian , Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260701094131.677636-1-linu.cherian@arm.com> <20260701094131.677636-4-linu.cherian@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20260701094131.677636-4-linu.cherian@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 01/07/26 3:11 PM, Linu Cherian wrote: > Add cputype definitions for Cortex-A520AE. > > The definition can be found in Cortex-A520AE TRM, > https://developer.arm.com/documentation/107726/0001/ > as part of MIDR_EL1 bit descriptions. > > This is going to be used in the bbml3 support list. > > Signed-off-by: Linu Cherian > --- > arch/arm64/include/asm/cputype.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index 1b9f0cda1336..e41fae46426b 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -82,6 +82,7 @@ > #define ARM_CPU_PART_CORTEX_X1 0xD44 > #define ARM_CPU_PART_CORTEX_A510 0xD46 > #define ARM_CPU_PART_CORTEX_A520 0xD80 > +#define ARM_CPU_PART_CORTEX_A520AE 0xD88 Part number checks out in the TRM > #define ARM_CPU_PART_CORTEX_A710 0xD47 > #define ARM_CPU_PART_CORTEX_A715 0xD4D > #define ARM_CPU_PART_CORTEX_X2 0xD48 > @@ -176,6 +177,7 @@ > #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) > #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) > #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520) > +#define MIDR_CORTEX_A520AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520AE) > #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) > #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) > #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) Reviewed-by: Anshuman Khandual