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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5de5f3f92ccsm5041174a12.66.2025.02.10.09.13.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 09:14:02 -0800 (PST) Message-ID: Date: Mon, 10 Feb 2025 18:13:58 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] drm/msm/dsi: Allow all bpc values To: Konrad Dybcio , Marijn Suijten , Danila Tikhonov Cc: neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, jonathan@marek.ca, jun.nie@linaro.org, fekz115@gmail.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux@mainlining.org, ~postmarketos/upstreaming@lists.sr.ht References: <20250203181436.87785-1-danila@jiaxyga.com> <20250203181436.87785-4-danila@jiaxyga.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: bYW6mh6PmCQV_iZgp5YbZ1xFrWdOcq7g X-Proofpoint-GUID: bYW6mh6PmCQV_iZgp5YbZ1xFrWdOcq7g X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_09,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 mlxscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100140 On 10.02.2025 6:10 PM, Konrad Dybcio wrote: > On 8.02.2025 11:09 PM, Marijn Suijten wrote: >> On 2025-02-03 21:14:26, Danila Tikhonov wrote: >>> From: Eugene Lepshy >>> >>> DRM DSC helper has parameters for various bpc values ​​other than 8: >> >> Weird zero-width \u200b spaces here between "values" and "other", please delete >> those. >> >>> (8/10/12/14/16). >>> >>> Remove this guard. >>> >>> Signed-off-by: Eugene Lepshy >>> Signed-off-by: Danila Tikhonov >> >> Should this patch elaborate that those "DRM DSC helper" don't have any >> additional guarding for the values you mention either, i.e. passing 9 or 11 or >>> 16 don't seem to be checked anywhere else either? >> >> And your title might have space to spell out "Bits Per Component" entirely. >> >>> --- >>> drivers/gpu/drm/msm/dsi/dsi_host.c | 7 +------ >>> 1 file changed, 1 insertion(+), 6 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c >>> index 007311c21fda..d182af7bbb81 100644 >>> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c >>> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c >>> @@ -1767,11 +1767,6 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc >>> return -EINVAL; >>> } >>> >>> - if (dsc->bits_per_component != 8) { >>> - DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n"); >>> - return -EOPNOTSUPP; >>> - } >>> - >>> dsc->simple_422 = 0; >>> dsc->convert_rgb = 1; >>> dsc->vbr_enable = 0; >> >> This seems supicous on the dpu1 side, in the original DSC 1.1 (not 1.2) block in >> dpu_hw_dsc_config(), which has: >> >> data |= (dsc->line_buf_depth << 3); >> data |= (dsc->simple_422 << 2); >> data |= (dsc->convert_rgb << 1); >> data |= dsc->bits_per_component; >> >> The original value of `8` would overlap with the lowest bit of line_buf_depth >> (4th bit in `data`). Now, the 2nd bit which will take the value from >> convert_rgb, which is already set to 1 above, will overlap with the 2nd bit in >> your new bpc value of 10. >> >> Can you double-check that this code in DPU1 is actually valid? I assume you >> have tested this panel at least and it is working (worthy mention in the cover >> letter?), this just seems like yet another mistake in the original bindings >> (though the register always had a matching value with downstream on 8 BPC panels >> for me). > > It seems like the lowest bit should be set iff the input is 10bpc, the > current situation where our '8' bleeds into the following (correctly named > fields) is bad. See also https://github.com/Wikidepia/kernel_xiaomi_santoni-4.9/blob/master/drivers/gpu/drm/msm/sde/sde_hw_dsc.c#L67-L80 Konrad