From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82580C43464 for ; Fri, 18 Sep 2020 08:13:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1ED522100A for ; Fri, 18 Sep 2020 08:13:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b="OKpSv9Ki" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726316AbgIRINB (ORCPT ); Fri, 18 Sep 2020 04:13:01 -0400 Received: from mx1.tq-group.com ([62.157.118.193]:5163 "EHLO mx1.tq-group.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726154AbgIRINA (ORCPT ); Fri, 18 Sep 2020 04:13:00 -0400 X-Greylist: delayed 367 seconds by postgrey-1.27 at vger.kernel.org; Fri, 18 Sep 2020 04:12:59 EDT IronPort-SDR: Tj5PpekTCSDUGI6qp58za9xUdVnv8QfrskXiee7JYAezdrga31XU7L9vZXGWR8PdpXrMRup+aL 0DlqOWxsjJia+eoFf9apYPnbRDWnpDu98rAVFDwLmeGs8D7kyU/DYVcyNO4i28BhpHSmBec1Pv rxVWg82MDRGr/KBKhdMigGUOvviLYTHS4/iQGDYHPAJgHRZtxBmPw1N0UrVr8U6woPMyutMuZg s5wlTJRGWNNz39snlLzd1f/qrkZXMituP6C/ArvC18BcJ082/2CJrOgDS9pbUoz2pKuoY0rjYe aW0= X-IronPort-AV: E=Sophos;i="5.77,274,1596492000"; d="scan'208";a="13919670" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 18 Sep 2020 10:06:51 +0200 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Fri, 18 Sep 2020 10:06:51 +0200 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Fri, 18 Sep 2020 10:06:51 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1600416411; x=1631952411; h=message-id:subject:from:to:cc:date:in-reply-to: references:mime-version:content-transfer-encoding; bh=wyZzvMMDTWnpQFctSpVvEtrwx5dWh5GhDZNJNn8DXGY=; b=OKpSv9KipQLGvLhaisXve1f4YdtGBCECRLzjV4cJDdUEw9Inz3pY1rAq rfvaZgp1NpMXwcEY9SBZPGJlGEJ3cb35oE1d0U3ojr052RU/GbEZv/W0i FQgoAttuWT+NIzIj0jdab8kh95dtHGrw3Lzt1iczheS+kuBbql9pV0LIr jl0yahfROKIcZZnmbV5T1imxfLvYntd+NjWFvEFL7n7hZRqdNhTUmqdtE YyV+r3gS0wG57gbFSihdSovV6Xw2PA9q6UuRufDOjftvE3I2P+dBlJSPs 0LApeuRbNWVdGEHb1dnd4Mf+pJs+Qtgb96IBZipoElUUh2h8Z+azMJGCk g==; IronPort-SDR: bEUj7A7obHd7zLLR1KFO4CAosz0TkLyVtyu2gPZcuStNxCLv7LuaPMtjKx6/zakGxXVOUiRtNo LhxEVcWzeBKluruXosnkzXIKfkcftngLBIvFU1DQ5nNbPdF7rEB2qzlvyktG5UMZsNLCXgOEAB LkND/kdJzuOEflD2Q465t9FC/mzjddbHPqkrL+iqn4WeG501TvrCP1OR+CKkMHIv6gXGwnpe1m kRnaGAUInaOZH+bQ9VzA41ucPHfWS01NxLSd61yalLcmgcWotFBnssWaWrnGzoyU/FeA1FJfuB 3Js= X-IronPort-AV: E=Sophos;i="5.77,274,1596492000"; d="scan'208";a="13919669" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 18 Sep 2020 10:06:51 +0200 Received: from schifferm-ubuntu4.tq-net.de (schifferm-ubuntu4.tq-net.de [10.117.48.12]) by vtuxmail01.tq-net.de (Postfix) with ESMTPA id 1EE5A280070; Fri, 18 Sep 2020 10:06:51 +0200 (CEST) Message-ID: Subject: Re: [PATCH] drm: fsl-dcu: enable PIXCLK on LS1021A From: Matthias Schiffer To: Stefan Agner , sboyd@kernel.org, mturquette@baylibre.com Cc: Alison Wang , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Date: Fri, 18 Sep 2020 10:06:48 +0200 In-Reply-To: <0321e3b1a9def003322b71f2a5fdfe08@agner.ch> References: <20200820105832.22331-1-matthias.schiffer@ew.tq-group.com> <0321e3b1a9def003322b71f2a5fdfe08@agner.ch> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2020-08-21 at 15:41 +0200, Stefan Agner wrote: > Hi Matthias, > > On 2020-08-20 12:58, Matthias Schiffer wrote: > > The PIXCLK needs to be enabled in SCFG before accessing the DCU on LS1021A, > > or the access will hang. > > Hm, this seems a rather ad-hoc access to SCFG from the DCU. We do > support a pixel clock in the device tree bindings of fsl-dcu, so ideally > we should enable the pixel clock through the clock framework. > > On the other hand, I guess that would mean adding a clock driver to flip > a single bit, which seems a bit excessive too. > > I'd like a second opinion on that. Adding clk framework maintainers. > > -- > Stefan How do we proceed with this patch? Kind regards, Matthias > > > > > Signed-off-by: Matthias Schiffer > > --- > > drivers/gpu/drm/fsl-dcu/Kconfig | 1 + > > drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 25 +++++++++++++++++++++++ > > drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 3 +++ > > 3 files changed, 29 insertions(+) > > > > diff --git a/drivers/gpu/drm/fsl-dcu/Kconfig b/drivers/gpu/drm/fsl-dcu/Kconfig > > index d7dd8ba90e3a..9e5a35e7c00c 100644 > > --- a/drivers/gpu/drm/fsl-dcu/Kconfig > > +++ b/drivers/gpu/drm/fsl-dcu/Kconfig > > @@ -8,6 +8,7 @@ config DRM_FSL_DCU > > select DRM_PANEL > > select REGMAP_MMIO > > select VIDEOMODE_HELPERS > > + select MFD_SYSCON if SOC_LS1021A > > help > > Choose this option if you have an Freescale DCU chipset. > > If M is selected the module will be called fsl-dcu-drm. > > diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c > > b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c > > index abbc1ddbf27f..8a7556655581 100644 > > --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c > > +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c > > @@ -51,6 +51,23 @@ static const struct regmap_config fsl_dcu_regmap_config = { > > .volatile_reg = fsl_dcu_drm_is_volatile_reg, > > }; > > > > +static int fsl_dcu_scfg_config_ls1021a(struct device_node *np) > > +{ > > + struct regmap *scfg; > > + > > + scfg = syscon_regmap_lookup_by_compatible("fsl,ls1021a-scfg"); > > + if (IS_ERR(scfg)) > > + return PTR_ERR(scfg); > > + > > + /* > > + * For simplicity, enable the PIXCLK unconditionally. It might > > + * be possible to disable the clock in PM or on unload as a future > > + * improvement. > > + */ > > + return regmap_update_bits(scfg, SCFG_PIXCLKCR, SCFG_PIXCLKCR_PXCEN, > > + SCFG_PIXCLKCR_PXCEN); > > +} > > + > > static void fsl_dcu_irq_uninstall(struct drm_device *dev) > > { > > struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; > > @@ -70,6 +87,14 @@ static int fsl_dcu_load(struct drm_device *dev, > > unsigned long flags) > > return ret; > > } > > > > + if (of_device_is_compatible(fsl_dev->np, "fsl,ls1021a-dcu")) { > > + ret = fsl_dcu_scfg_config_ls1021a(fsl_dev->np); > > + if (ret < 0) { > > + dev_err(dev->dev, "failed to enable pixclk\n"); > > + goto done; > > + } > > + } > > + > > ret = drm_vblank_init(dev, dev->mode_config.num_crtc); > > if (ret < 0) { > > dev_err(dev->dev, "failed to initialize vblank\n"); > > diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h > > b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h > > index e2049a0e8a92..566396013c04 100644 > > --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h > > +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h > > @@ -160,6 +160,9 @@ > > #define FSL_DCU_ARGB4444 12 > > #define FSL_DCU_YUV422 14 > > > > +#define SCFG_PIXCLKCR 0x28 > > +#define SCFG_PIXCLKCR_PXCEN BIT(31) > > + > > #define VF610_LAYER_REG_NUM 9 > > #define LS1021A_LAYER_REG_NUM 10