Re: [PATCH] dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible

[Michal Simek <michal.simek@amd.com>]

Hi Conor,

On 11/6/23 12:37, Michal Simek wrote:
> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
> It is hardware compatible with classic MicroBlaze processor.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
>   Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 97e8441eda1c..7b077af62b27 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -32,6 +32,7 @@ properties:
>       oneOf:
>         - items:
>             - enum:
> +              - amd,mbv32
>                 - andestech,ax45mp
>                 - canaan,k210
>                 - sifive,bullet0

Can you please queue this patch to your tree?

Thanks,
Michal