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Perttunen To: Thierry Reding , Svyatoslav Ryhel Cc: Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH v1 3/6] dt-bindings: display: tegra: Document 8-bit CPU parallel interface Date: Fri, 02 Oct 2026 14:58:07 +0900 Message-ID: In-Reply-To: References: <20260930070535.47130-1-clamor95@gmail.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-ClientProxiedBy: TYCP286CA0060.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b5::15) To SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: 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X5fMeviREp/FT3RAQravlNN1EjoGasVH6xIHZgcjwxsnIkqGP6SEkdDI1xNgq0jsAUif25sBSf+Xx+fcVdAxXg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5887 On Thursday, October 1, 2026 3:03=E2=80=AFAM Svyatoslav Ryhel wrote: > =D1=81=D1=80, 30 =D0=B2=D0=B5=D1=80. 2026=E2=80=AF=D1=80. =D0=BE 12:19 Mi= kko Perttunen =D0=BF=D0=B8=D1=88=D0=B5: > > > > On Wednesday, September 30, 2026 4:05=E2=80=AFPM Svyatoslav Ryhel wrote= : > > > Document 8-bit CPU parallel MIPI DBI Type B interface provided by > > > Tegra20/30 SoCs display controller. > > > > > > Signed-off-by: Svyatoslav Ryhel > > > --- > > > .../display/tegra/nvidia,tegra-8bit-cpu.yaml | 138 ++++++++++++++++= ++ > > > 1 file changed, 138 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/display/tegra/n= vidia,tegra-8bit-cpu.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,t= egra-8bit-cpu.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia= ,tegra-8bit-cpu.yaml > > > new file mode 100644 > > > index 0000000000000..f0dab608b2936 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-8b= it-cpu.yaml > > > @@ -0,0 +1,138 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra-8bit-c= pu.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Nvidia Tegra DC based MIPI DBI Type B bridge > > > + > > > +maintainers: > > > + - Svyatoslav Ryhel > > > + > > > +description: The display controller in Tegra20/30 SoCs features an > > > + 8-bit SPI interface that closely resembles the MIPI DBI Type B > > > + protocol and is referred to as '8-bit CPU'. Each display controlle= r > > > + provides two such interfaces, which can be used to send MIPI DCS > > > + commands to initialize and control the panel while image data is > > > + transmitted via 16/18/24-line RGB. > > > + > > > +properties: > > > + compatible: > > > + const: nvidia,tegra-8bit-cpu > > > + > > > + dc-gpios: > > > + description: Data/command selection pin. > > > + maxItems: 1 > > > + > > > + rw-gpios: > > > + description: Read/write pin. > > > + maxItems: 1 > > > + > > > + cs-gpios: > > > + description: Chip select pin. > > > + maxItems: 1 > > > + > > > + data-gpios: > > > + description: Specifies a set of 8 gpio pins used to transfer dat= a. > > > + minItems: 8 > > > + maxItems: 8 > > > > Based on my admittedly brief research, according to the TRM the display > > controller can drive all of these pins - of which there are two fixed > > sets as you mention - directly. So we'd need to describe which interfac= e > > the display is connected to in DT, but not any GPIOs (which they really > > aren't). > > >=20 > Thierry, Mikko. >=20 > I am not sure how to approach GPIOs defined outside of Device Tree. > All GPIO interactions are done either by ofnode/fwnode or software > nodes. Global gpio declaration is in process of being removed and > legacy GPIO API seem to be not long-therm sustainable. How to resolve > this? Should I keep above layout with GPIOs defined in the tree? I looked a bit closer and I now think the initialization sequences=20 cannot be done entirely through the display controller - so this is=20 correct, we do need the GPIO stuff. >=20 > > > + > > > + nvidia,init-sequence: > > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > > + description: Device specific set of values used in DC DISP_SPI_I= NIT_SEQ > > > + registers. > > > + minItems: 4 > > > + maxItems: 4 > > > > And AIUI this is panel-specific DBI commands the display controller wil= l > > transmit. So ideally the display driver should receive this data from > > the panel driver. > > > > Thank you > > Mikko > > > > > + > > > + panel: > > > + type: object > > > + description: Node of supported panel driven by the bridge. > > > + > > > + ports: > > > + $ref: /schemas/graph.yaml#/properties/ports > > > + > > > + properties: > > > + port@0: > > > + $ref: /schemas/graph.yaml#/$defs/port-base > > > + unevaluatedProperties: false > > > + description: Video port for RGB input. > > > + > > > + properties: > > > + endpoint: > > > + $ref: /schemas/graph.yaml#/$defs/endpoint-base > > > + unevaluatedProperties: false > > > + > > > + properties: > > > + bus-width: > > > + enum: [ 16, 18, 24 ] > > > + > > > + port@1: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: Video port for DBI output (panel or connector). > > > + > > > + required: > > > + - port@0 > > > + - port@1 > > > + > > > +required: > > > + - compatible > > > + - ports > > > + > > > +unevaluatedProperties: false > > > + > > > +examples: > > > + - | > > > + #include > > > + > > > + dbi-bridge { > > > + compatible =3D "nvidia,tegra-8bit-cpu"; > > > + > > > + dc-gpios =3D <&gpio 110 GPIO_ACTIVE_HIGH>; > > > + rw-gpios =3D <&gpio 11 GPIO_ACTIVE_HIGH>; > > > + cs-gpios =3D <&gpio 108 GPIO_ACTIVE_HIGH>; > > > + > > > + data-gpios =3D <&gpio 32 GPIO_ACTIVE_HIGH>, <&gpio 33 GPIO_A= CTIVE_HIGH>, > > > + <&gpio 34 GPIO_ACTIVE_HIGH>, <&gpio 35 GPIO_ACT= IVE_HIGH>, > > > + <&gpio 36 GPIO_ACTIVE_HIGH>, <&gpio 37 GPIO_ACT= IVE_HIGH>, > > > + <&gpio 38 GPIO_ACTIVE_HIGH>, <&gpio 39 GPIO_ACT= IVE_HIGH>; > > > + > > > + nvidia,init-sequence =3D <0x0000002c 0x0 0x0 0x00005000>; > > > + > > > + panel { > > > + compatible =3D "hit,tx10d07vm0baa"; > > > + > > > + reset-gpios =3D <&gpio 175 GPIO_ACTIVE_LOW>; > > > + > > > + avci-supply =3D <&vcc_2v8_lcd>; > > > + iovcc-supply =3D <&iovcc_1v8_lcd>; > > > + > > > + backlight =3D <&backlight>; > > > + > > > + port { > > > + panel_input: endpoint { > > > + remote-endpoint =3D <&bridge_output>; > > > + }; > > > + }; > > > + }; > > > + > > > + ports { > > > + #address-cells =3D <1>; > > > + #size-cells =3D <0>; > > > + > > > + port@0 { > > > + reg =3D <0>; > > > + > > > + bridge_input: endpoint { > > > + remote-endpoint =3D <&dpi_output>; > > > + }; > > > + }; > > > + > > > + port@1 { > > > + reg =3D <1>; > > > + > > > + bridge_output: endpoint { > > > + remote-endpoint =3D <&panel_input>; > > > + }; > > > + }; > > > + }; > > > + }; > > > -- > > > 2.53.0 > > > > > > > > > > > > > >