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Thu, 25 Sep 2025 01:57:42 -0700 (PDT) Message-ID: Date: Thu, 25 Sep 2025 11:57:41 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Kaanapali SoC To: Jingyi Wang , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Raviteja Laggyshetty Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com References: <20250924-knp-interconnect-v1-0-4c822a72141c@oss.qualcomm.com> <20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com> From: Eugen Hristev Content-Language: en-US In-Reply-To: <20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 9/25/25 02:02, Jingyi Wang wrote: > From: Raviteja Laggyshetty > > Document the RPMh Network-On-Chip Interconnect of the Kaanapali platform. > > Signed-off-by: Raviteja Laggyshetty > Signed-off-by: Jingyi Wang > --- > .../bindings/interconnect/qcom,kaanapali-rpmh.yaml | 126 +++++++++++++++++ > .../dt-bindings/interconnect/qcom,kaanapali-rpmh.h | 149 +++++++++++++++++++++ > 2 files changed, 275 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interconnect/qcom,kaanapali-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,kaanapali-rpmh.yaml > new file mode 100644 > index 000000000000..574150cc4930 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interconnect/qcom,kaanapali-rpmh.yaml > @@ -0,0 +1,126 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interconnect/qcom,kaanapali-rpmh.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm RPMh Network-On-Chip Interconnect on KAANAPALI > + > +maintainers: > + - Raviteja Laggyshetty > + > +description: | > + RPMh interconnect providers support system bandwidth requirements through > + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is > + able to communicate with the BCM through the Resource State Coordinator (RSC) > + associated with each execution environment. Provider nodes must point to at > + least one RPMh device child node pertaining to their RSC and each provider > + can map to multiple RPMh resources. > + > + See also: include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h > + > +properties: > + compatible: > + enum: > + - qcom,kaanapali-aggre-noc Hi, Does Kaanapali have a single aggre node, or there are several ? On previous SoC, I see there are two (aggre1 and aggre2). Also in your driver (second patch), I notice aggre1_noc and aggre2_noc . It would make sense to accurately describe here the hardware. Eugen > + - qcom,kaanapali-clk-virt > + - qcom,kaanapali-cnoc-main > + - qcom,kaanapali-cnoc-cfg > + - qcom,kaanapali-gem-noc > + - qcom,kaanapali-lpass-ag-noc > + - qcom,kaanapali-lpass-lpiaon-noc > + - qcom,kaanapali-lpass-lpicx-noc > + - qcom,kaanapali-mc-virt > + - qcom,kaanapali-mmss-noc > + - qcom,kaanapali-nsp-noc > + - qcom,kaanapali-pcie-anoc > + - qcom,kaanapali-system-noc > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 2 > + maxItems: 3 > + > +required: > + - compatible > + > +allOf: > + - $ref: qcom,rpmh-common.yaml# > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,kaanapali-clk-virt > + - qcom,kaanapali-mc-virt > + then: > + properties: > + reg: false > + else: > + required: > + - reg > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,kaanapali-pcie-anoc > + then: > + properties: > + clocks: > + items: > + - description: aggre-NOC PCIe AXI clock > + - description: cfg-NOC PCIe a-NOC AHB clock > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,kaanapali-aggre-noc > + then: > + properties: > + clocks: > + items: > + - description: aggre UFS PHY AXI clock > + - description: aggre USB3 PRIM AXI clock > + - description: RPMH CC IPA clock > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,kaanapali-aggre-noc > + - qcom,kaanapali-pcie-anoc > + then: > + required: > + - clocks > + else: > + properties: > + clocks: false > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + clk_virt: interconnect-0 { > + compatible = "qcom,kaanapali-clk-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + aggre_noc: interconnect@16e0000 { > + compatible = "qcom,kaanapali-aggre-noc"; > + reg = <0x016e0000 0x42400>; > + #interconnect-cells = <2>; > + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&rpmhcc RPMH_IPA_CLK>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > diff --git a/include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h b/include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h > new file mode 100644 > index 000000000000..dde3f9abd677 > --- /dev/null > +++ b/include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h > @@ -0,0 +1,149 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KAANAPALI_H > +#define __DT_BINDINGS_INTERCONNECT_QCOM_KAANAPALI_H > + > +#define MASTER_QSPI_0 0 > +#define MASTER_CRYPTO 1 > +#define MASTER_QUP_1 2 > +#define MASTER_SDCC_4 3 > +#define MASTER_UFS_MEM 4 > +#define MASTER_USB3 5 > +#define MASTER_QUP_2 6 > +#define MASTER_QUP_3 7 > +#define MASTER_QUP_4 8 > +#define MASTER_IPA 9 > +#define MASTER_SOCCP_PROC 10 > +#define MASTER_SP 11 > +#define MASTER_QDSS_ETR 12 > +#define MASTER_QDSS_ETR_1 13 > +#define MASTER_SDCC_2 14 > +#define SLAVE_A1NOC_SNOC 15 > +#define SLAVE_A2NOC_SNOC 16 > + > +#define MASTER_QUP_CORE_0 0 > +#define MASTER_QUP_CORE_1 1 > +#define MASTER_QUP_CORE_2 2 > +#define MASTER_QUP_CORE_3 3 > +#define MASTER_QUP_CORE_4 4 > +#define SLAVE_QUP_CORE_0 5 > +#define SLAVE_QUP_CORE_1 6 > +#define SLAVE_QUP_CORE_2 7 > +#define SLAVE_QUP_CORE_3 8 > +#define SLAVE_QUP_CORE_4 9 > + > +#define MASTER_CNOC_CFG 0 > +#define SLAVE_AHB2PHY_SOUTH 1 > +#define SLAVE_AHB2PHY_NORTH 2 > +#define SLAVE_CAMERA_CFG 3 > +#define SLAVE_CLK_CTL 4 > +#define SLAVE_CRYPTO_0_CFG 5 > +#define SLAVE_DISPLAY_CFG 6 > +#define SLAVE_EVA_CFG 7 > +#define SLAVE_GFX3D_CFG 8 > +#define SLAVE_I2C 9 > +#define SLAVE_I3C_IBI0_CFG 10 > +#define SLAVE_I3C_IBI1_CFG 11 > +#define SLAVE_IMEM_CFG 12 > +#define SLAVE_IPC_ROUTER_CFG 13 > +#define SLAVE_CNOC_MSS 14 > +#define SLAVE_PCIE_CFG 15 > +#define SLAVE_PRNG 16 > +#define SLAVE_QDSS_CFG 17 > +#define SLAVE_QSPI_0 18 > +#define SLAVE_QUP_1 19 > +#define SLAVE_QUP_2 20 > +#define SLAVE_QUP_3 21 > +#define SLAVE_QUP_4 22 > +#define SLAVE_SDCC_2 23 > +#define SLAVE_SDCC_4 24 > +#define SLAVE_SPSS_CFG 25 > +#define SLAVE_TCSR 26 > +#define SLAVE_TLMM 27 > +#define SLAVE_UFS_MEM_CFG 28 > +#define SLAVE_USB3 29 > +#define SLAVE_VENUS_CFG 30 > +#define SLAVE_VSENSE_CTRL_CFG 31 > +#define SLAVE_CNOC_MNOC_CFG 32 > +#define SLAVE_PCIE_ANOC_CFG 33 > +#define SLAVE_QDSS_STM 34 > +#define SLAVE_TCU 35 > + > +#define MASTER_GEM_NOC_CNOC 0 > +#define MASTER_GEM_NOC_PCIE_SNOC 1 > +#define SLAVE_AOSS 2 > +#define SLAVE_IPA_CFG 3 > +#define SLAVE_IPC_ROUTER_FENCE 4 > +#define SLAVE_SOCCP 5 > +#define SLAVE_TME_CFG 6 > +#define SLAVE_APPSS 7 > +#define SLAVE_CNOC_CFG 8 > +#define SLAVE_DDRSS_CFG 9 > +#define SLAVE_BOOT_IMEM 10 > +#define SLAVE_IMEM 11 > +#define SLAVE_PCIE_0 12 > + > +#define MASTER_GPU_TCU 0 > +#define MASTER_SYS_TCU 1 > +#define MASTER_APPSS_PROC 2 > +#define MASTER_GFX3D 3 > +#define MASTER_LPASS_GEM_NOC 4 > +#define MASTER_MSS_PROC 5 > +#define MASTER_MNOC_HF_MEM_NOC 6 > +#define MASTER_MNOC_SF_MEM_NOC 7 > +#define MASTER_COMPUTE_NOC 8 > +#define MASTER_ANOC_PCIE_GEM_NOC 9 > +#define MASTER_QPACE 10 > +#define MASTER_SNOC_SF_MEM_NOC 11 > +#define MASTER_WLAN_Q6 12 > +#define MASTER_GIC 13 > +#define SLAVE_GEM_NOC_CNOC 14 > +#define SLAVE_LLCC 15 > +#define SLAVE_MEM_NOC_PCIE_SNOC 16 > + > +#define MASTER_LPIAON_NOC 0 > +#define SLAVE_LPASS_GEM_NOC 1 > + > +#define MASTER_LPASS_LPINOC 0 > +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1 > + > +#define MASTER_LPASS_PROC 0 > +#define SLAVE_LPICX_NOC_LPIAON_NOC 1 > + > +#define MASTER_LLCC 0 > +#define SLAVE_EBI1 1 > + > +#define MASTER_CAMNOC_HF 0 > +#define MASTER_CAMNOC_NRT_ICP_SF 1 > +#define MASTER_CAMNOC_RT_CDM_SF 2 > +#define MASTER_CAMNOC_SF 3 > +#define MASTER_MDP 4 > +#define MASTER_MDSS_DCP 5 > +#define MASTER_CDSP_HCP 6 > +#define MASTER_VIDEO_CV_PROC 7 > +#define MASTER_VIDEO_EVA 8 > +#define MASTER_VIDEO_MVP 9 > +#define MASTER_VIDEO_V_PROC 10 > +#define MASTER_CNOC_MNOC_CFG 11 > +#define SLAVE_MNOC_HF_MEM_NOC 12 > +#define SLAVE_MNOC_SF_MEM_NOC 13 > +#define SLAVE_SERVICE_MNOC 14 > + > +#define MASTER_CDSP_PROC 0 > +#define SLAVE_CDSP_MEM_NOC 1 > + > +#define MASTER_PCIE_ANOC_CFG 0 > +#define MASTER_PCIE_0 1 > +#define SLAVE_ANOC_PCIE_GEM_NOC 2 > +#define SLAVE_SERVICE_PCIE_ANOC 3 > + > +#define MASTER_A1NOC_SNOC 0 > +#define MASTER_A2NOC_SNOC 1 > +#define MASTER_APSS_NOC 2 > +#define MASTER_CNOC_SNOC 3 > +#define SLAVE_SNOC_GEM_NOC_SF 4 > + > +#endif >