From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932939AbdKOX74 convert rfc822-to-8bit (ORCPT ); Wed, 15 Nov 2017 18:59:56 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1107 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932182AbdKOX7q (ORCPT ); Wed, 15 Nov 2017 18:59:46 -0500 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 15 Nov 2017 15:59:45 -0800 From: Daniel Lustig To: Palmer Dabbelt , "will.deacon@arm.com" CC: Arnd Bergmann , Olof Johansson , "linux-kernel@vger.kernel.org" , "patches@groups.riscv.org" , "peterz@infradead.org" , "boqun.feng@gmail.com" Subject: RE: [patches] Re: [PATCH v9 05/12] RISC-V: Atomic and Locking Code Thread-Topic: [patches] Re: [PATCH v9 05/12] RISC-V: Atomic and Locking Code Thread-Index: AQHTNzSE3QqwrlfQIkmQw8nmHNJn0aLzNUyAgCFrQYCAAWnUgIAAHIKAgAA5JRA= Date: Wed, 15 Nov 2017 23:59:44 +0000 Message-ID: References: <20171115180600.GR19071@arm.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.110.39.40] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Wed, 15 Nov 2017 10:06:01 PST (-0800), will.deacon@arm.com wrote: >> On Tue, Nov 14, 2017 at 12:30:59PM -0800, Palmer Dabbelt wrote: >> > On Tue, 24 Oct 2017 07:10:33 PDT (-0700), will.deacon@arm.com wrote: >> >>On Tue, Sep 26, 2017 at 06:56:31PM -0700, Palmer Dabbelt wrote: > > > > Hi Palmer, > > > >> >>+ATOMIC_OPS(add, add, +, i, , _relaxed) > >> >>+ATOMIC_OPS(add, add, +, i, .aq , _acquire) ATOMIC_OPS(add, add, > >> >>++, i, .rl , _release) > >> >>+ATOMIC_OPS(add, add, +, i, .aqrl, ) > >> > > >> >Have you checked that .aqrl is equivalent to "ordered", since there > >> >are interpretations where that isn't the case. Specifically: > >> > > >> >// all variables zero at start of time > >> >P0: > >> >WRITE_ONCE(x) = 1; > >> >atomic_add_return(y, 1); > >> >WRITE_ONCE(z) = 1; > >> > > >> >P1: > >> >READ_ONCE(z) // reads 1 > >> >smp_rmb(); > >> >READ_ONCE(x) // must not read 0 > >> > >> I haven't. We don't quite have a formal memory model specification yet. > >> I've added Daniel Lustig, who is creating that model. He should have > >> a better idea > > > > Thanks. You really do need to ensure that, as it's heavily relied upon. > > I know it's the case for our current processors, and I'm pretty sure it's the > case for what's formally specified, but we'll have to wait for the spec in order > to prove it. I think Will is right. In the current spec, using .aqrl converts an RCpc load or store into an RCsc load or store, but the acquire(-RCsc) annotation still only applies to the load part of the atomic, and the release(-RCsc) annotation applies only to the store part of the atomic. Why is that? Picture an machine which implements AMOs using something that looks more like an LR/SC under the covers, or one that uses cache line locking, or anything else along those same lines. In some such machines, there could be a window between lock/reserve and unlock/store-conditional where other later stores could squeeze into, and that would break Will's example among others. It's likely the same reasoning that causes ARM to use a trailing dmb here, rather than just using ldaxr/stlxr. Is that right Will? I know that's LL/SC and this particular cases uses AMOADD, but it's the same principle. Well, at least according to how we have it in the current memory model draft. Also, RISC-V currently prefers leading fence mappings, so I think the result here, for atomic_add_return() for example, should be this: fence rw,rw amoadd.aq ... Note that at this point, I think you could even elide the .rl. If I'm reading it right it looks like the ARM mapping does this too (well, the reverse: ARM elides the "a" in ldaxr due to the trailing dmb making it redundant). Does that seem reasonable to you all? Dan