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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abba9bd6e22sm1409071066b.121.2025.02.24.03.46.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Feb 2025 03:46:47 -0800 (PST) Message-ID: Date: Mon, 24 Feb 2025 12:46:44 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/2] phy: qcom: qmp-pcie: Add PHY register retention support To: "Wenbin Yao (Consultant)" , Manivannan Sadhasivam Cc: vkoul@kernel.org, kishon@kernel.org, p.zabel@pengutronix.de, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, quic_qianyu@quicinc.com, neil.armstrong@linaro.org, quic_devipriy@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250220102253.755116-1-quic_wenbyao@quicinc.com> <20250220102253.755116-3-quic_wenbyao@quicinc.com> <20250224073301.aqbw3gxjnupbejfy@thinkpad> <7ffb09cd-9c77-4407-9087-3e789cd8bf44@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <7ffb09cd-9c77-4407-9087-3e789cd8bf44@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: Av8E--Hb1DuKbim8vTgm9deyhZSRFB9D X-Proofpoint-ORIG-GUID: Av8E--Hb1DuKbim8vTgm9deyhZSRFB9D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-24_05,2025-02-24_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 bulkscore=0 impostorscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502240086 On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote: > On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote: >> On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote: >>> From: Qiang Yu >>> >>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the >>> whole PHY (hardware and register), no_csr reset only resets PHY hardware >>> but retains register values, which means PHY setting can be skipped during >>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled >>> after that. >>> >>> Hence, determine whether the PHY has been enabled in bootloader by >>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is >>> available, skip BCR reset and PHY register setting to establish the PCIe >>> link with bootloader - programmed PHY settings. >>> >>> Signed-off-by: Qiang Yu >>> Signed-off-by: Wenbin Yao >> Some nitpicks below. >> >>> --- [...] >> >>> +     * In this way, no matter whether the PHY settings were initially >>> +     * programmed by bootloader or PHY driver itself, we can reuse them >> It is really possible to have bootloader not programming the init sequence for >> no_csr reset platforms? The comment sounds like it is possible. But I heard the >> opposite. > > PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it > manually in UEFI shell if we want. IIUC this will not be a concern going forward, and this is a special case Konrad