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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SpfTwNtgS3QNEJwVpcCninDSXshXur2LhADBqYRrIHWoX9b7xOyXAtAc6AY3/pfOlmlapF9fBjMgztu9ejd2q6EIjMne1UxQ+SrGSLxkocRx7s3h5J8l0oeYN8e+tlcw2AgItrY1A8qNhD8ucI8pcM+ZbHOnb/oiCGCmGM1GEXYaDwWzRpb0Fvj6v0yUupIVS41q/0TUj3tJXpqrKTTi32SWDKEbB74IqO2CslNJ/rp/JlJtovIKdORnRY2tlUeX3GWHtBIgS0L6WMWsWAOIT5JXfEuS+1NflLMtobk1JG1KLVNYcSydMCHu2B5J5YmcrZFeX7UyeuYkh8Kkm9XSghXmnLnq8JE6pFAVfBIoK89MEiOSFEs/jgS+Q+YYbQl6eTVyG0WKSdfb720IpDXjuYmMIdDbvA9gcCt+VLkMmDDDegOkjkWKqzqSYYbn42qw X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2026 06:19:57.5008 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6eb2f5e3-7b7e-4756-4b22-08df0d7134a2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00005FFC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6989 Hello Mario, On 9/8/2026 9:49 AM, Mario Limonciello (AMD) wrote: > +/* > + * The numeric EPP value programmed for each named preference. First dimension > + * is CPU type (TOPO_CPU_TYPE_ANY for non-hybrid, TOPO_CPU_TYPE_PERFORMANCE/ > + * EFFICIENCY/LOW_POWER for hybrid). The initializer holds the legacy values > + * used as the fallback on any platform not listed in amd_pstate_epp_soc_ids[]; > + * amd_pstate_init_epp_values() overwrites slots at boot when the running SoC > + * has a per-SoC (and potentially per-CPU-type) override. > + */ > +static u8 epp_values[][EPP_INDEX_MAX] = { > + [TOPO_CPU_TYPE_ANY] = { > + [EPP_INDEX_DEFAULT] = 0, > + [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_LEGACY_PERFORMANCE, > + [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMANCE, > + [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, > + [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_LEGACY_POWERSAVE, > + }, > + [TOPO_CPU_TYPE_PERFORMANCE] = { > + [EPP_INDEX_DEFAULT] = 0, > + [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_LEGACY_PERFORMANCE, > + [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMANCE, > + [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, > + [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_LEGACY_POWERSAVE, > + }, > + [TOPO_CPU_TYPE_EFFICIENCY] = { > + [EPP_INDEX_DEFAULT] = 0, > + [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_LEGACY_PERFORMANCE, > + [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMANCE, > + [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, > + [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_LEGACY_POWERSAVE, > + }, > + [TOPO_CPU_TYPE_LOW_POWER] = { > + [EPP_INDEX_DEFAULT] = 0, > + [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_LEGACY_PERFORMANCE, > + [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMANCE, > + [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, > + [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_LEGACY_POWERSAVE, > + }, > +}; If my eyes aren't decieveing me, all the indices are initialized to same value so we can perhaps do: static u8 epp_values[][EPP_INDEX_MAX] = { /* * Initialize all CPU types to legacy defaults. * amd_pstate_init_epp_values() will fix these up * based on the platform during boot. */ [TOPO_CPU_TYPE_ANY ... TOPO_CPU_TYPE_LOW_POWER] = { [EPP_INDEX_DEFAULT] = 0, [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_LEGACY_PERFORMANCE, [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_LEGACY_BALANCE_PERFORMANCE, [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_LEGACY_BALANCE_POWERSAVE, [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_LEGACY_POWERSAVE, }, }; > +static_assert(ARRAY_SIZE(epp_values) == TOPO_CPU_TYPE_LOW_POWER + 1, > + "epp_values must have entries for all CPU types up to TOPO_CPU_TYPE_LOW_POWER"); > + > +/* > + * Get the EPP value row for a given CPU, accounting for hybrid CPU types. > + * Non-hybrid systems use TOPO_CPU_TYPE_ANY; hybrid systems use the CPU's > + * actual type (PERFORMANCE/EFFICIENCY/LOW_POWER). > + */ > +static inline u8 *amd_pstate_cpu_epp_values(int cpu) > +{ > + enum x86_topology_cpu_type type = cpu_data(cpu).topo.cpu_type; Can we cache this in cpudata to avoid an additional dereference? > + I would prefer a: if (!cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) return epp_values[TOPO_CPU_TYPE_ANY]; here to avoid the branches for non-heterogenoeus platforms. > + if (type == TOPO_CPU_TYPE_PERFORMANCE || > + type == TOPO_CPU_TYPE_EFFICIENCY || > + type == TOPO_CPU_TYPE_LOW_POWER) > + return epp_values[type]; > + > + return epp_values[TOPO_CPU_TYPE_ANY]; A switch case might look prettier ;-) > +} -- Thanks and Regards, Prateek