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Wed, 30 Apr 2025 00:02:59 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53U02wXK005737 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Apr 2025 00:02:58 GMT Received: from [10.134.71.99] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 29 Apr 2025 17:02:58 -0700 Message-ID: Date: Tue, 29 Apr 2025 17:02:58 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/8] drm/msm/dpu: don't select single flush for active CTL blocks To: Dmitry Baryshkov , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter CC: , , , , "Neil Armstrong" References: <20250307-dpu-active-ctl-v3-0-5d20655f10ca@linaro.org> <20250307-dpu-active-ctl-v3-5-5d20655f10ca@linaro.org> Content-Language: en-US From: Jessica Zhang In-Reply-To: <20250307-dpu-active-ctl-v3-5-5d20655f10ca@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=B7i50PtM c=1 sm=1 tr=0 ts=681168b3 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=aUBE8IUH5cRvplel0kQA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: giJQVt-oUb7P0Kb65lxEDyjTOQkVRR8e X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI5MDE3OCBTYWx0ZWRfX6lLc25Sakqmp P0FiwD6F5wDxbnWeAkZGnzh77FmOpY/XT5DKzZd0Mn1NUBpptEyfn7XkAVWAU7+YAetYSZDKXC/ RZe2DeFzglMYDq3dCRPs4VgYuh30E5PKnsl1JAI2+XUQd0BFx/DellA7seQNFGWurPj2h+dPQv2 o9Ct1pgbyj6Mie91cOLpM6XrADyg1KyTgJn4hSKZYTpKIfwF4Za3384cgdLkPHqIN4YBkENfwcz YQ8S7l0o0/35y4FYhzQe/ZN4BPF7RpF9V2xyoS2xLhuMrY1v2pUWNycnPblbaFXtJoyvt8ZQzLM kFnNhRfI+ykrYM9v9QbLv4ahY3BtXbo9ls6+dzeDl0daIzKxl5+o8LnKu8iy5VnE/UhALSD9lO6 URBfN5oEcx5JB/OxbefogjZFiDGPROfRU8or+Gc/D7IMDAdx7zSD7swldroIce+8RZemfNOt X-Proofpoint-ORIG-GUID: giJQVt-oUb7P0Kb65lxEDyjTOQkVRR8e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-29_08,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 spamscore=0 clxscore=1015 mlxscore=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504290178 On 3/6/2025 10:24 PM, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov > > In case of ACTIVE CTLs, a single CTL is being used for flushing all INTF > blocks. Don't skip programming the CTL on those targets. > > Tested-by: Neil Armstrong # on SM8550-QRD > Signed-off-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > index 232055473ba55998b79dd2e8c752c129bbffbff4..8a618841e3ea89acfe4a42d48319a6c54a1b3495 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > @@ -374,7 +374,8 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg) > static bool dpu_encoder_phys_vid_needs_single_flush( > struct dpu_encoder_phys *phys_enc) > { > - return phys_enc->split_role != ENC_ROLE_SOLO; > + return !(phys_enc->hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) && > + phys_enc->split_role != ENC_ROLE_SOLO; > } > > static void dpu_encoder_phys_vid_atomic_mode_set( >