From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40CB8C4338F for ; Tue, 3 Aug 2021 03:51:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2239860187 for ; Tue, 3 Aug 2021 03:51:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233736AbhHCDvT (ORCPT ); Mon, 2 Aug 2021 23:51:19 -0400 Received: from foss.arm.com ([217.140.110.172]:42544 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233719AbhHCDvN (ORCPT ); Mon, 2 Aug 2021 23:51:13 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3219511D4; Mon, 2 Aug 2021 20:51:02 -0700 (PDT) Received: from [10.163.67.68] (unknown [10.163.67.68]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8FF773F70D; Mon, 2 Aug 2021 20:50:58 -0700 (PDT) Subject: Re: [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures To: Marc Zyngier Cc: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, mark.rutland@arm.com References: <20210728135217.591173-1-suzuki.poulose@arm.com> <20210728135217.591173-11-suzuki.poulose@arm.com> <87mtq5a1gs.wl-maz@kernel.org> <477c4943-7c35-8502-0291-4c0ed3a03905@arm.com> <32f719c8f9f61b244b3fc29137f76a19@kernel.org> From: Anshuman Khandual Message-ID: Date: Tue, 3 Aug 2021 09:21:48 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <32f719c8f9f61b244b3fc29137f76a19@kernel.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/2/21 3:05 PM, Marc Zyngier wrote: > On 2021-08-02 10:12, Anshuman Khandual wrote: >> On 7/29/21 4:11 PM, Suzuki K Poulose wrote: >>> On 29/07/2021 10:55, Marc Zyngier wrote: >>>> On Wed, 28 Jul 2021 14:52:17 +0100, >>>> Suzuki K Poulose > > [...] > >>>>> +            __tsb_csync();                        \ >>>>> +            __tsb_csync();                        \ >>>>> +        } else {                            \ >>>>> +            __tsb_csync();                        \ >>>>> +        }                                \ >>>> >>>> nit: You could keep one unconditional __tsb_csync(). >>> >>> I thought about that, I was worried if the CPU expects them back to back >>> without any other instructions in between them. Thinking about it a bit >>> more, it doesn't look like that is the case. I will confirm this and >>> change it accordingly. >> But its a very subtle change which might be difficult to debug and blame >> later on, if indeed both the instructions need to be back to back. Seems >> like just better to leave this unchanged. > > Is that an actual requirement? Sounds like you want to find out > from the errata document. Sure, will get back on this. > > And if they actually need to be back to back, what ensures that > this is always called with interrupt disabled? > > You would also need to have them in the same asm block to avoid > the compiler reordering stuff. Agreed, both the above constructs will be required to make sure that the instructions will be executed consecutively (if required).