From: "Kathpalia, Tanmay" <tanmay.kathpalia@altera.com>
To: tze.yee.ng@altera.com, Adrian Hunter <adrian.hunter@intel.com>,
Ulf Hansson <ulfh@kernel.org>,
linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH 1/4] mmc: sdhci-cadence6: add PHY settle delay after tuning DLL re-lock
Date: Sat, 26 Sep 2026 16:14:06 +0530 [thread overview]
Message-ID: <eb04492f-fecc-4470-974c-8417613a2278@altera.com> (raw)
In-Reply-To: <a0edc86ec30949ca7b923f4939a911960e8b5395.1790074790.git.tze.yee.ng@altera.com>
On 22-09-2026 16:42, tze.yee.ng@altera.com wrote:
> From: Tze Yee Ng<tze.yee.ng@altera.com>
>
> After re-locking the DLL, allow the same 5 to 5.5 ms for the clock and
> PHY signals to stabilize as sdhci_cdns6_phy_init() does. Without this
> settle time the command issued immediately after tuning (e.g. the R1b
> CMD6 that switches eMMC from HS200 down to HS during HS400 selection)
> can time out.
One additional concern is that the testing listed in the cover letter
does not
exercise the paths described here. The series reports testing SD DDR50
and eMMC
DDR52, but neither mode performs tuning through sdhci_cdns6_set_tune_val().
Please test this change with eMMC HS200 and HS400. The same function is also
used during SD SDR104 tuning, so SDR104 should be covered as well.
next prev parent reply other threads:[~2026-09-26 10:44 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-22 11:12 [PATCH 0/4] mmc: sdhci-cadence: SD6HC DDR50 read-path tuning and fixes tze.yee.ng
2026-09-22 11:12 ` [PATCH 1/4] mmc: sdhci-cadence6: add PHY settle delay after tuning DLL re-lock tze.yee.ng
2026-09-24 6:41 ` Adrian Hunter
2026-09-24 8:49 ` Kathpalia, Tanmay
2026-09-26 10:44 ` Kathpalia, Tanmay [this message]
2026-09-22 11:12 ` [PATCH 2/4] mmc: sdhci-cadence6: program PHONY_DQS_TIMING for extended-read DDR tze.yee.ng
2026-09-24 6:41 ` Adrian Hunter
2026-09-26 10:45 ` Kathpalia, Tanmay
2026-09-22 11:12 ` [PATCH 3/4] dt-bindings: mmc: cdns,sdhci: add SD6HC DDR50 read-path tuning tze.yee.ng
2026-09-26 10:48 ` Kathpalia, Tanmay
2026-09-22 11:12 ` [PATCH 4/4] mmc: sdhci-cadence: read SD6HC DDR50 tuning from device tree tze.yee.ng
2026-09-24 6:40 ` Adrian Hunter
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