Re: [PATCH v2 1/2] dt-bindings: pwm: Add Xilinx AXI Timer

[Michal Simek <michal.simek@xilinx.com>]

On 5/6/21 11:10 PM, Sean Anderson wrote:
> 
> 
> On 5/6/21 5:05 PM, Rob Herring wrote:
>> On Tue, May 04, 2021 at 02:49:24PM -0400, Sean Anderson wrote:
>>> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is
>>> a "soft" block, so it has many parameters which would not be
>>> configurable in most hardware. This binding is usually automatically
>>> generated by Xilinx's tools, so the names and values of properties
>>> must be kept as they are.
>>>
>>> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
>>> ---
>>>
>>> Changes in v2:
>>> - Use 32-bit addresses for example binding
>>>
>>>   .../bindings/pwm/xlnx,axi-timer.yaml          | 91 +++++++++++++++++++
>>>   1 file changed, 91 insertions(+)
>>>   create mode 100644
> Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml
>>>
>>> diff --git
> a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml
> b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml
>>> new file mode 100644
>>> index 000000000000..bd014134c322
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml
>>> @@ -0,0 +1,91 @@
>>> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding
>>> +
>>> +maintainers:
>>> +  - Sean Anderson <sean.anderson@seco.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    items:
>>> +      - const: xlnx,axi-timer-2.0
>>> +      - const: xlnx,xps-timer-1.00.a
>>> +
>>> +  clocks:
>>> +    maxItems: 1
>>> +
>>> +  clock-names:
>>> +    const: s_axi_aclk
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +  xlnx,count-width:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    minimum: 8
>>> +    maximum: 32
>>> +    description:
>>> +      The width of the counters, in bits.
>>> +
>>> +  xlnx,gen0-assert:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    enum: [ 0, 1 ]
>>> +    description:
>>> +      The polarity of the generateout0 signal. 0 for active-low, 1
> for active-high.
>>> +
>>> +  xlnx,gen1-assert:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    enum: [ 0, 1 ]
>>> +    description:
>>> +      The polarity of the generateout1 signal. 0 for active-low, 1
> for active-high.
>>> +
>>> +  xlnx,one-timer-only:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    enum: [ 0, 1 ]
>>> +    description:
>>> +      Whether only one timer is present in this block.
>>> +
>>> +  xlnx,trig0-assert:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    enum: [ 0, 1 ]
>>> +    description:
>>> +      The polarity of the capturetrig0 signal. 0 for active-low, 1
> for active-high.
>>> +
>>> +  xlnx,trig1-assert:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    enum: [ 0, 1 ]
>>> +    description:
>>> +      The polarity of the capturetrig1 signal. 0 for active-low, 1
> for active-high.
>>
>> Can't all these be boolean?
> 
> They could, but
> 
>> This binding is usually automatically generated by Xilinx's tools, so
>> the names and values of properties must be kept as they are.
> 
> Because this is a soft device, the binding may be (very conveniently)
> auto-generated. I am not opposed to adding additional properties which
> could be used by new code, but we should still accept this auto-generated
> output.

I think in this case you should described what it is used by current
driver in Microblaze and these options are required. The rest are by
design optional.
If you want to change them to different value then current binding
should be deprecated and have any transition time with code alignment.

Thanks,
Michal