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	id 1uPO4S-00FQMS-G7; Wed, 11 Jun 2025 18:13:00 +0200
Date: Wed, 11 Jun 2025 18:13:00 +0200
From: Andrew Lunn <andrew@lunn.ch>
To: Inochi Amaoto <inochiama@gmail.com>
Cc: Andrew Lunn <andrew+netdev@lunn.ch>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Chen Wang <unicorn_wang@outlook.com>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alex@ghiti.fr>,
	netdev@vger.kernel.org, devicetree@vger.kernel.org,
	sophgo@lists.linux.dev, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, Yixun Lan <dlan@gentoo.org>,
	Longbin Li <looong.bin@gmail.com>
Subject: Re: [PATCH net-next 2/2] net: mdio-mux: Add MDIO mux driver for
 Sophgo CV1800 SoCs
Message-ID: <eb419ffa-055f-48db-8c6a-60bf240fbb9d@lunn.ch>
References: <20250611080228.1166090-1-inochiama@gmail.com>
 <20250611080228.1166090-3-inochiama@gmail.com>
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In-Reply-To: <20250611080228.1166090-3-inochiama@gmail.com>

On Wed, Jun 11, 2025 at 04:02:00PM +0800, Inochi Amaoto wrote:
> Add device driver for the mux driver for Sophgo CV18XX/SG200X
> series SoCs.
> 
> @@ -0,0 +1,119 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Sophgo CV1800 MDIO multiplexer driver
> + *
> + * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <linux/delay.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/mdio-mux.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#define EPHY_PAGE_SELECT		0x07c
> +#define EPHY_CTRL			0x800
> +#define EPHY_REG_SELECT			0x804
> +
> +#define EPHY_PAGE_SELECT_SRC		GENMASK(12, 8)
> +
> +#define EPHY_CTRL_ANALOG_SHUTDOWN	BIT(0)
> +#define EPHY_CTRL_USE_EXTPHY		BIT(7)
> +#define EPHY_CTRL_PHYMODE		BIT(8)
> +#define EPHY_CTRL_PHYMODE_SMI_RMII	1
> +#define EPHY_CTRL_EXTPHY_ID		GENMASK(15, 11)

There are a lot of defines here which are not used, but as far as i
see, there is one 8bit register, where bit 7 controls the mux.

It looks like you can throw this driver away and just use
mdio-mux-mmioreg.c. This is from the binding documentation with a few
tweaks:

   mdio-mux@3009000 {
        compatible = "mdio-mux-mmioreg", "mdio-mux";
        mdio-parent-bus = <&xmdio0>;
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x3009000 1>;
        mux-mask = <128>;

        mdio@0 {
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <0>;

            phy_xgmii_slot1: ethernet-phy@4 {
                compatible = "ethernet-phy-ieee802.3-c45";
                reg = <4>;
            };
        };

        mdio@128 {
            reg = <128>;
            #address-cells = <1>;
            #size-cells = <0>;

            ethernet-phy@4 {
                compatible = "ethernet-phy-ieee802.3-c45";
                reg = <4>;
            };
        };
    };

    Andrew