From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752084AbeAWSJT (ORCPT ); Tue, 23 Jan 2018 13:09:19 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:45136 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751979AbeAWSJP (ORCPT ); Tue, 23 Jan 2018 13:09:15 -0500 Cc: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, Sudeep Holla , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, sboyd@codeaurora.org, rnayak@codeaurora.org, asathyak@codeaurora.org, devicetree@vger.kernel.org Subject: Re: [PATCH RFC 2/4] dt-bindings/interrupt-controller: pdc: descibe PDC device binding To: Lina Iyer References: <20180123175656.11942-1-ilina@codeaurora.org> <20180123175656.11942-3-ilina@codeaurora.org> From: Sudeep Holla Organization: ARM Message-ID: Date: Tue, 23 Jan 2018 18:09:11 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20180123175656.11942-3-ilina@codeaurora.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/01/18 17:56, Lina Iyer wrote: > From: Archana Sathyakumar > > Add device binding documentation for the PDC Interrupt controller on > QCOM SoC's like the SDM845. The interrupt-controller can be used to > sense edge low interrupts and wakeup interrupts when the GIC is > non-operational. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Archana Sathyakumar > Signed-off-by: Lina Iyer > --- > .../bindings/interrupt-controller/qcom,pdc.txt | 55 ++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt > new file mode 100644 > index 000000000000..c4592bbf678d > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt > @@ -0,0 +1,55 @@ > +PDC interrupt controller > + > +Qualcomm Technologies Inc. SoCs based on the RPM Hardened archicture have a > +Power Domain Controller (PDC) that is on always-on domain. In addition to > +providing power control for the power domains, the hardware also has an > +interrupt controller that can be used to help detect edge low interrupts as > +well detect interrupts when the GIC is non-operational. > + > +GIC is parent interrupt controller at the highest level. Platform interrupt > +controller PDC is next in hierarchy, followed by others. > This driver only configures the interrupts, does not handle them. Not sure if the above statement belongs to the binding. -- Regards, Sudeep