From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 847D93AD51A for ; Wed, 3 Jun 2026 10:27:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780482445; cv=none; b=Dq5PQwvYWWs1vYBcBR7BZBmureiJQkivZYY8JQP3CqWdGuxA40G2KXpu7O4ENwcUXDE3fJDU+ZcQL6zO7X2hSKWozlDa8/iinOZlhwWGHQIlk5TKBb44mIwH+JhKq1CW54FnO7SXuO30RqkQ5HIu7O1DzEIUCH/i1pOUlOQCauM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780482445; c=relaxed/simple; bh=6aL4l3Ur3jsCLfcmTxD3VhVZp8AyRsbYnFcCugx26NA=; h=Message-ID:Date:MIME-Version:Subject:From:To:Cc:References: In-Reply-To:Content-Type; b=qTdszJw3T0Zb0qHaSXUrYQmB47Cs0G26xA/tLxhaWy4QjfrOA23z7nlauIlI42iZmMCg++qIUKcZmjh6zqsSdI/AYCx+6vEs9ZrcaIFqOcUfm+b47cijXxP3cVlqBl4UYGiTg2fiMqBgguv1mSWmLY5nVWBiCh8Rh3tiWamtOEw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=EOjyakpe; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="EOjyakpe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1780482441; bh=6aL4l3Ur3jsCLfcmTxD3VhVZp8AyRsbYnFcCugx26NA=; h=Date:Subject:From:To:Cc:References:In-Reply-To:From; b=EOjyakpep+v7+Xow5oK32R8tPEBjHwdEeHbPheiYcss/3buxi01AAA7ua5JJIVn/j al2o63aRvF7fpplbvgGp3DVCVVolK1iQPAFLDD0FcgXyQPe3JEAqOn7e7bPuM8wFCW 9TDq+62/gZIMWiM+6P1GAhEv4TDw6/YrTQLi7WdEaIkiiWTT+YN8H1zFxNwLp4qeSy vKv/yOFhPl0Am0Nf59Dibe3/G4IOCPPajZjpnXLjNCDIdEl9aBXghMyGoFhtiHFfby qsP7qcGpRxQe5C1tUwbbSjq55T7eM7Ab3DnktF68go+WtfutOjV/ud8Sc9uf5KpfS/ LLVsjHPkgAVvA== Received: from [100.64.0.241] (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5678A17E05DE; Wed, 3 Jun 2026 12:27:21 +0200 (CEST) Message-ID: Date: Wed, 3 Jun 2026 13:27:20 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups From: Cristian Ciocaltea To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?Q?Thomas_Niederpr=C3=BCm?= , Simon Wright References: <20260511-hdptx-clk-fixes-v2-0-664e41379cab@collabora.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/20/26 10:05 PM, Cristian Ciocaltea wrote: > Hi Vinod, > > On 5/11/26 9:21 PM, Cristian Ciocaltea wrote: >> This series provides a set of bug fixes and cleanups for the Rockchip >> Samsung HDPTX PHY driver. >> >> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate >> calculation and synchronization issues. Specifically, it fixes edge >> cases where the PHY PLL is pre-programmed by an external component (like >> a bootloader) or when changing the color depth (bpc) while keeping the >> modeline constant. Because the Common Clock Framework .set_rate() >> callback might not be invoked if the pixel clock remains unchanged, this >> previously led to out-of-sync states between CCF and the actual HDMI PHY >> configuration. >> >> The second part focuses on code cleanups and modernizing the register >> access. Now that dw_hdmi_qp driver has fully switched to using >> phy_configure(), we can drop the deprecated TMDS rate setup workarounds >> and the restrict_rate_change flag logic. Finally, it refactors the >> driver to consistently use standard bitfield macros. >> >> Signed-off-by: Cristian Ciocaltea >> --- >> Changes in v2: >> - Collected Tested-by tags from Thomas and Simon >> - Fixed a typo in commit description of patch 1 >> - Added a comment in patch 2 explaining why PLL config errors are >> ignored for rk_hdptx_phy_consumer_get() >> - Added a missed FIELD_GET conversion for lcpll_hw.pms_sdiv in patch 6 >> - Rebased onto latest phy/fixes >> - Link to v1: https://lore.kernel.org/r/20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com > > In case you missed my comments from last week on the Sashiko AI review findings > - in short, I don't think there is anything to worry about and the series should > be fine to apply as-is. Please let me know if you would still prefer a new > revision. Kind reminder.. Regards, Cristian