From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757792AbeAHOBa (ORCPT + 1 other); Mon, 8 Jan 2018 09:01:30 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:19735 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757773AbeAHOB2 (ORCPT ); Mon, 8 Jan 2018 09:01:28 -0500 Subject: Re: [PATCH v5 01/44] dt-bindings: clock: Add new bindings for TI Davinci PLL clocks To: David Lechner , , , CC: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Kevin Hilman , Adam Ford , References: <1515377863-20358-1-git-send-email-david@lechnology.com> <1515377863-20358-2-git-send-email-david@lechnology.com> From: Sekhar Nori Message-ID: Date: Mon, 8 Jan 2018 19:30:13 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <1515377863-20358-2-git-send-email-david@lechnology.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Monday 08 January 2018 07:47 AM, David Lechner wrote: > This adds a new binding for the PLL IP blocks in the mach-davinci family > of processors. Currently, only the SYSCLKn and AUXCLK outputs are needed, > but in the future additional child nodes could be added for OBSCLK and > BPDIV. > > Note: Although these PLL controllers are very similar to the TI Keystone > SoCs, we are not re-using those bindings. The Keystone bindings use a > legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs Not sure what is meant by "legacy one-node-per-clock binding" > have a slightly different PLL register layout and a number of quirks that > can't be handled by the existing bindings, so the keystone bindings could > not be used as-is anyway. Right, I think different register layout between the processors is the main reason for a new driver. This should be sufficient reason IMO. > > Signed-off-by: David Lechner > --- > .../devicetree/bindings/clock/ti/davinci/pll.txt | 47 ++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/pll.txt > > diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt > new file mode 100644 > index 0000000..99bf5da > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt > @@ -0,0 +1,47 @@ > +Binding for TI DaVinci PLL Controllers > + > +The PLL provides clocks to most of the components on the SoC. In addition > +to the PLL itself, this controller also contains bypasses, gates, dividers, > +an multiplexers for various clock signals. > + > +Required properties: > +- compatible: shall be one of: > + - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX > + - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX These PLLs are same IP so they should use the same compatible. You can initialize both PLLs for DA850 based on the same compatible. Thanks, Sekhar