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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?yizhfWjMMxSF3NjmhikizE0ibVKCDSTcrnD0YHWWtW92TNpQN6/oP6QMDs+Y?= =?us-ascii?Q?VbV0q5WkyU2cd4OKS5UVkVk9Iil1nBg1LfmBy2SdSXDgM2g9rtNyPRov0IB1?= =?us-ascii?Q?aIMSDwEUt38EAGj6gGy17s0CqlP4/nejYw66wyck/g4VjIjYBFwfG98DqmiO?= =?us-ascii?Q?lZgp7TlZwrgGALLtko3ak5P1wt9P3ryk9ACkxTplelLHfhVa/ckjrMzWPG7I?= =?us-ascii?Q?g2V8MokcsF7aL0+d8ou2Fk8Gf0fvvlqE1t8NZCmQqfytCVZUtzj1xPRo0nOq?= =?us-ascii?Q?4tRUkqPhemXRsQ1D8y5P9+830F0eMiFDBm7R0HiioTL1XDwlA2JOQiahgDyy?= =?us-ascii?Q?Mgf8d4Heu8OB5XiVpFLGc+Hwj4qXBs2L7j1AOwi08JAQ4K6MTQcShB5nGF7u?= =?us-ascii?Q?CRSTTIqMWFHeFcBFTGZK/dc/YJntv9qVPrOMUy4mBuerH7XvHIvnWm4fwWeY?= =?us-ascii?Q?MbKvf1xZUj8k6WtQ9h/escbbwknJDjKlRMl03ACY3SkBI49RJioF0fq8dcyW?= =?us-ascii?Q?wLoWI1ukr46uB5pg4fjXyF4Ty4oB87ppOgwueY70Yp9625Twge0Nvj8Zpa08?= =?us-ascii?Q?MkoK+g4Vl5m34UWT11Pb2Ev5gu7uyyD7YKY5/qnJk1JlOeaITRacltYLR37g?= =?us-ascii?Q?nLzSDvg/iPpWYWF/MN55GDnnl/YydTg70AkzKKo1A0EbciHVSLyeZqWRaXSG?= =?us-ascii?Q?WSKi0fJbvEPNlS36skmY51069hpVoQ7/rYgM9NICp/v0wonB7ccy2psCqPkd?= =?us-ascii?Q?wboynkXyvXBOklglDabmdGN+6rdwb8AE8qmeEEfXq4fL2KuZpkiZy5Cf9Pgd?= =?us-ascii?Q?fKKgzExZ0jCd0GwGYcdvN3wVsCJ+6+NXD22NLoyG9fouHa9sVsRF+WDYXwQn?= =?us-ascii?Q?cElODQcX9bxfbJz+YnOfGiIObEavZTtKl1p+pqXmSA5+AGk6nx2354tjkbek?= =?us-ascii?Q?3KMlOOHypCpT/0BVPF95gaVNrYdza7agFu2C/afQbBqW+53y44KO8KTcKMuu?= =?us-ascii?Q?CS19h7doZL6dOPaIJQiH73VsrGMoul3sSVjM83FjTO8ZT2anceNBqujRBMv0?= =?us-ascii?Q?6o5P5GhiOPu2AvVpjyMdjxsVVrQrx0p8FjKccdOCFy+07cqweEA8VnfD3Rnr?= =?us-ascii?Q?1tu+axvMCao0SIQqhTXstQSliQVijzIQ9N3ypPJHff0hOFa9GGd61fvIUw2k?= =?us-ascii?Q?iJd+EkjwUOshWuniGwhv5o+W8TjQX1vcfgHLmiMk8M4DNuVTAW+Hx2hddzCT?= =?us-ascii?Q?AgXAm5+MOtHlsbZXyyMmGHiIxE+EM8r0ypcvagpaNXeaVa7Yg0FgUKUP7OVz?= =?us-ascii?Q?uFgCYj7mxnTElrl5/z5qoxmW057bKOljlzUtyWBAATabL/Xlne6+dpUAZ6nX?= =?us-ascii?Q?7VgD45dZTsdORu6ddrePkTIkVrGBmBxDiqd7FoinQ1y1qD2IJI/euDhB7zxf?= =?us-ascii?Q?l4bkRz85CvC5NVe0BqiaVEFYz2PONojZvX4tU+33DQu1tG64C7QV0NrQLizU?= =?us-ascii?Q?AJoTE2225c0dKxkfMjsLcZb/d/zTHgpzy2t+WfGsU7ZCWTsOIki23C6oqcBW?= =?us-ascii?Q?3Itz6ks3U7X3kxZMsVaITTEbvuppX7Ip+gMuCBf79q6tBHEfD47io4CJhTOG?= =?us-ascii?Q?pugYBqN0eLyyag7MsPbJ480=3D?= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0445d817-3157-48d6-67ed-08dc59fa059b X-MS-Exchange-CrossTenant-AuthSource: BL0PR01MB4226.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2024 07:35:55.1945 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7xBj3ur0cod0l/Vym9Ku+x1qmm1H+ddG2tT1cBeL6OHnYiUBZZjUSciJnFPRsIy2bjuiRbdw5gA4jD3STONemgkweZyJQa72Kd0wz9WuCg7Zgpeic32dNbMFFIIUy74N X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR01MB8411 On Tue, 9 Apr 2024, Robin Murphy wrote: > On 09/04/2024 2:05 am, Ilkka Koskinen wrote: >> >> On Mon, 8 Apr 2024, Robin Murphy wrote: >>> On 2024-04-05 11:33 pm, Ilkka Koskinen wrote: >>>> >>>> On Fri, 5 Apr 2024, Robin Murphy wrote: >>>>> On 2024-03-07 7:31 pm, Ilkka Koskinen wrote: >>>>>> The driver enabled and disabled interrupts even if no interrupt was >>>>>> assigned to the device. >>>>> >>>>> Why's that a concern - if the interrupt isn't routed anywhere, surely it >>>>> makes no difference what happens at the source end? >>>> >>>> The issue is that we have two PMUs attached to the same interrupt line. >>>> Unfortunately, I just don't seem to find time to add support for shared >>>> interrupts to the cspmu driver. Meanwhile, I assigned the interrupt to >>>> one of the PMUs while the other one has zero in the APMT table. >>> >>> I suspected something like that ;) >>> >>>> Without the patch, I can trigger "ghost interrupt" in the latter PMU. >>> >>> An occasional spurious interrupt should be no big deal. If it ends up as a >>> screaming spurious interrupt because we never handle the overflow >>> condition on the "other" PMU, then what matters most is that we never >>> handle the overflow, thus the "other" PMU is still useless since you can't >>> assume the user is going to read it frequently enough to avoid losing >>> information and getting nonsense counts back. So this hack really isn't a >>> viable solution for anything. >> >> IIRC, what happens is that kernel will disable the interrupt eventually due >> to unhandled spurious interrupts making the "working" PMU also useless. > > Indeed, but if having one inaccurate PMU is fine, having more than one is no > big deal either, right? The moral of the story is that hacking the firmware > to lie about the hardware is just not a great idea. Depends on the use case, of course :D > > TBH it's always seemed a bit broken that we allow probing without an IRQ but > then have no accommodation for overflow if so. Fixing that would be a good > thing in itself, and would at least have the side-effect of allowing your > hack to work, however much I may disapprove of that :) > > FWIW it is still lingering some way down my to-do list to factor out the > fiddly IRQ-sharing/migration code into at least a helper library (if not > further into perf core itself) before it gets copy-pasted much more, and it > occurs to me that I could then easily factor the IRQ-substitute timer > approach from e.g. arm-ccn into that as well... The more I think about it the > more I might just convince myself that I want it for the driver I'm currently > working on and justify bumping it up the list, let's see... That sounds like a great idea. Even plain helper library would keep the drivers a lot cleaner. Cheers, Ilkka