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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id ay3-20020a5d6f03000000b0033d1b760125sm8742879wrb.92.2024.02.18.14.59.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 18 Feb 2024 14:59:07 -0800 (PST) Message-ID: Date: Sun, 18 Feb 2024 23:59:07 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/2] clocksource/drivers/arm_global_timer: Fix maximum prescaler value Content-Language: en-US To: Martin Blumenstingl , tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andrea.merello@gmail.com, patrice.chotard@foss.st.com, linux-amlogic@lists.infradead.org References: <20240218174138.1942418-1-martin.blumenstingl@googlemail.com> <20240218174138.1942418-2-martin.blumenstingl@googlemail.com> From: Daniel Lezcano In-Reply-To: <20240218174138.1942418-2-martin.blumenstingl@googlemail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 18/02/2024 18:41, Martin Blumenstingl wrote: > The prescaler in the "Global Timer Control Register bit assignments" is > documented to use bits [15:8], which means that the maximum prescaler > register value is 0xff. > > Fixes: 171b45a4a70e ("clocksource/drivers/arm_global_timer: Implement rate compensation whenever source clock changes") > Signed-off-by: Martin Blumenstingl > --- > drivers/clocksource/arm_global_timer.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c > index 44a61dc6f932..e1c773bb5535 100644 > --- a/drivers/clocksource/arm_global_timer.c > +++ b/drivers/clocksource/arm_global_timer.c > @@ -32,7 +32,7 @@ > #define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */ > #define GT_CONTROL_AUTO_INC BIT(3) /* banked */ > #define GT_CONTROL_PRESCALER_SHIFT 8 > -#define GT_CONTROL_PRESCALER_MAX 0xF > +#define GT_CONTROL_PRESCALER_MAX 0xFF > #define GT_CONTROL_PRESCALER_MASK (GT_CONTROL_PRESCALER_MAX << \ > GT_CONTROL_PRESCALER_SHIFT Good catch! IMO the initial confusion is coming from the shift and the mask size. But should GT_CONTROL_PRESCALER_MAX be 256 ? so (0xFF + 1) The following may be less confusing: #define GT_CONTROL_PRESCALER_SHIFT 8 #define GT_CONTROL_PRESCALER_MASK GENMASK(15,8) #define GT_CONTROL_PRESCALER_MAX (GT_CONTROL_PRESCALER_MASK >> \ GT_CONTROL_PRESCALER_SHIFT) + 1 -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog