From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751368AbdAWSXY (ORCPT ); Mon, 23 Jan 2017 13:23:24 -0500 Received: from foss.arm.com ([217.140.101.70]:51764 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750756AbdAWSXW (ORCPT ); Mon, 23 Jan 2017 13:23:22 -0500 Subject: Re: [PATCH 1/4] PCI: Xilinx NWL: Fix, do not check for legacy status in while loop To: Bharat Kumar Gogada , bhelgaas@google.com, paul.gortmaker@windriver.com, robh@kernel.org, colin.king@canonical.com, linux-pci@vger.kernel.org References: <1484997072-19276-1-git-send-email-bharatku@xilinx.com> Cc: michal.simek@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, rgummal@xilinx.com, arnd@arndb.de, Bharat Kumar Gogada From: Marc Zyngier Organization: ARM Ltd Message-ID: Date: Mon, 23 Jan 2017 18:23:17 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Icedove/45.5.1 MIME-Version: 1.0 In-Reply-To: <1484997072-19276-1-git-send-email-bharatku@xilinx.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/01/17 11:11, Bharat Kumar Gogada wrote: > - The legacy status register value for particular INTx becomes low > only after DEASSERT_INTx is received. > - Few End Points take time for sending DEASSERT_INTx, checking > legacy status register in while loop causes invoking of EP > handler continuosly until DEASSERT_INTx is received. > > Signed-off-by: Bharat Kumar Gogada > --- > drivers/pci/host/pcie-xilinx-nwl.c | 5 +++-- > 1 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c > index 43eaa4a..c8b5a33 100644 > --- a/drivers/pci/host/pcie-xilinx-nwl.c > +++ b/drivers/pci/host/pcie-xilinx-nwl.c > @@ -342,9 +342,10 @@ static void nwl_pcie_leg_handler(struct irq_desc *desc) > > chained_irq_enter(chip, desc); > pcie = irq_desc_get_handler_data(desc); > + status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & > + MSGF_LEG_SR_MASKALL; > > - while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & > - MSGF_LEG_SR_MASKALL) != 0) { > + if (status != 0) { > for_each_set_bit(bit, &status, INTX_NUM) { > virq = irq_find_mapping(pcie->legacy_irq_domain, > bit + 1); > But even if you only handle the interrupt once, it is still asserted, right? You exit the low-level exception handler, only to take the interrupt immediately again. So what is the gain here? As an aside, please add a cover letter to your patch series. It is immensely useful as a summary of what is being done, as well as an anchor for the patches themselves. Thanks, M. -- Jazz is not dead. It just smells funny...